IP Library Granted Patent US 12,495,652
Granted Patent B2
US 12,495,652 · App. 18/039,326 · Granted Dec 9, 2025

Semiconductor light emitting device and supporting substrate for semiconductor light emitting elements

Inventors: Keima Kono (Tokyo, JP); Koji Ichikawa (Tokyo, JP); Daizo Kambara (Tokyo, JP); Naochika Horio (Tokyo, JP)
Assignee: STANLEY ELECTRIC CO., LTD.
H10H20/857
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Quick Facts
Patent No.
US 12,495,652
App. No.
18/039,326
Granted
Dec 9, 2025
Kind
B2
Abstract

A semiconductor light emitting device includes a semiconductor light emitting laminate, and an SOI substrate including an upper semiconductor layer, an interlayer insulating film, and a lower semiconductor layer. The SOI substrate includes a first wiring electrode provided on the upper semiconductor layer through an insulating film and corresponding to a p-electrode, a second wiring electrode connected to the upper semiconductor layer and corresponding to an n-electrode, an anode that is provided on the lower semiconductor layer and connected to a first wiring electrode by a first via electrode passing through the SOI substrate, a cathode that is provided on the lower semiconductor layer through an insulating film and connected to the upper semiconductor layer by a second via electrode reaching the upper semiconductor layer. The p-electrode and the n-electrode are respectively bonded to the first wiring electrode and the second wiring electrode.

Claims (26)

1 . A semiconductor light emitting device comprising:

a semiconductor light emitting laminate in which a first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer are laminated, and that is provided with at least one first element electrode connected to the first semiconductor layer and at least one second element electrode connected to the second semiconductor layer on a surface on the first semiconductor layer side; and

an SOI substrate that comprises an upper semiconductor layer, a lower semiconductor layer, and an interlayer insulating film provided between the upper semiconductor layer and the lower semiconductor layer,

wherein:

the SOI substrate includes:

at least one first wiring electrode that is provided on the upper semiconductor layer through an insulating film and corresponds to the at least one first element electrode of the semiconductor light emitting element, and at least one second wiring electrode that is provided on the upper semiconductor layer by being connected to the upper semiconductor layer and corresponds to the at least one second element electrode of the semiconductor light emitting laminate,

a first mounting electrode that is provided on the lower semiconductor layer and connected to the at least one first wiring electrode by a first via electrode passing through the SOI substrate, and

a second mounting electrode that is provided on the lower semiconductor layer through the insulating film and connected to the upper semiconductor layer by a second via electrode passing through the lower semiconductor layer and the interlayer insulating film to reach the upper semiconductor layer, and

the at least one first element electrode and the at least one second element electrode of the semiconductor light emitting laminate are respectively bonded to the at least one first wiring electrode and the at least one second wiring electrode of the SOI substrate.

2 . The semiconductor light emitting device according to claim 1 , wherein the upper semiconductor layer and the lower semiconductor layer are n-Si layers, and the lower semiconductor layer is connected to the first mounting electrode and includes an impurity diffusion region that is provided on a front surface of the lower semiconductor layer, and is connected to the second mounting electrode to form a pn bonding in the lower semiconductor layer.

3 . The semiconductor light emitting device according to claim 1 , wherein the first conductive type and the second conductive type are p-type and n-type, respectively, and the at least one second element electrode is provided on the second semiconductor layer exposed from a via reaching the second semiconductor layer from a front surface of the first semiconductor layer.

4 . The semiconductor light emitting device according to claim 1 , wherein the first conductive type and the second conductive type are p-type and n-type, respectively, and the at least one first element electrode includes a translucent conductive film and a reflective film.

5 . The semiconductor light emitting device according to claim 1 , wherein the semiconductor light emitting laminate includes a plurality of the second element electrodes, and the plurality of second element electrodes are disposed at symmetrical positions on the surface of the first semiconductor layer side.

6 . The semiconductor light emitting device according to claim 1 , wherein the first element electrode is formed as a full-surface electrode over an entire surface of the first semiconductor layer except for a region of the at least one second wiring electrode.

7 . The semiconductor light emitting device according to claim 1 , further comprising:

a metal electrode layer that is provided on the upper semiconductor layer and connected to the at least one second wiring electrode.

8 . The semiconductor light emitting device according to claim 7 , wherein the metal electrode layer is formed over an entire surface of the upper semiconductor layer.

9 . A supporting substrate for mounting a semiconductor light emitting element that includes first and second semiconductor layers each having first and second conductive types, and a light emitting layer provided between the first and second semiconductor layers, and that is provided with at least one first electrode connected to the first semiconductor layer and at least one second electrode connected to the second semiconductor layer on one surface side, the supporting substrate comprising:

an SOI substrate that is formed of an upper semiconductor layer, a lower semiconductor layer, and an interlayer insulating film provided between the upper semiconductor layer and the lower semiconductor layer,

wherein the SOI substrate includes:

at least one first wiring electrode that is provided on the upper semiconductor layer through an insulating film and corresponds to the at least one first electrode of the semiconductor light emitting element, and at least one second wiring electrode that is provided on the upper semiconductor layer by being connected to the upper semiconductor layer and corresponds to the at least one second electrode of the semiconductor light emitting laminate,

a first mounting electrode that is provided on the lower semiconductor layer and connected to the at least one first wiring electrode by a first via electrode passing through the SOI substrate, and

a second mounting electrode that is provided on the lower semiconductor layer through the insulating film and connected to the upper semiconductor layer by a second via electrode passing through the lower semiconductor layer and the interlayer insulating film to reach the upper semiconductor layer.

10 . The supporting substrate according to claim 9 , wherein the upper semiconductor layer and the lower semiconductor layer are n-Si layers, and the lower semiconductor layer is connected to the first mounting electrode and includes an impurity diffusion region that is provided on a front surface of the lower semiconductor layer, and is connected to the second mounting electrode to form a pn bonding in the lower semiconductor layer.

11 . The supporting substrate according to claim 9 , further comprising:

a metal electrode layer that is provided on the upper semiconductor layer and connected to the at least one second wiring electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2023
From: KONO, KEIMA; ICHIKAWA, KOJI; KAMBARA, DAIZO; HORIO, NAOCHIKA
To: STANLEY ELECTRIC CO., LTD.
Reel/Frame 063790/0545 →
Priority Claims (1)
JP 2020-205024 · Dec 10, 2020 · national
Continuity (1)
Related Publication 20240021767A1 · Jan 18, 2024
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