Isolation structures of semiconductor devices
A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.
1 . A semiconductor device, comprising:
a substrate including:
a bulk layer;
a buried insulator layer over the bulk layer; and
a semiconductor layer over the buried insulator layer;
a first gate electrode over the substrate;
a second gate electrode laterally adjacent to the first gate electrode; and
an isolation structure in contact with the first gate electrode and the second gate electrode, and the isolation structure extends into the substrate and terminates within the bulk layer thereof.
2 . The semiconductor device of claim 1 , wherein the bulk layer of the substrate comprises a doped region, and the isolation structure extends through the doped region.
3 . The semiconductor device of claim 1 , wherein the bulk layer of the substrate comprises a doped region, and the isolation structure terminates within the doped region.
4 . The semiconductor device of claim 1 , wherein the buried insulator layer has a first side surface, the semiconductor layer has a second side surface, the first gate electrode has a third side surface, and the first side surface, the second side surface, and the third side surface are substantially coplanar with each other.
5 . The semiconductor device of claim 1 , wherein the isolation structure comprises:
a dielectric core having laterally opposite side surfaces; and
a dielectric liner at least on the laterally opposite side surfaces of the dielectric core.
6 . The semiconductor device of claim 5 , wherein the dielectric core comprises a first dielectric material and the dielectric liner includes a second dielectric material having a higher dielectric constant than the first dielectric material.
7 . The semiconductor device of claim 1 , further comprising:
a first contact structure over the first gate electrode, the first contact structure having a first upper surface; and
a second contact structure in the isolation structure, the second contact structure having a second upper surface, and the first upper surface and the second upper surface are substantially coplanar with each other.
8 . The semiconductor device of claim 7 , wherein the first contact structure has a first depth from the first upper surface thereof and the second contact structure has a second depth from the second upper surface thereof, and the second depth is deeper than the first depth.
9 . The semiconductor device of claim 7 , further comprising:
a dielectric layer over the substrate, wherein the first contact structure, the second contact structure, and a portion of the isolation structure are arranged in the dielectric layer.
10 . A semiconductor device, comprising:
a substrate;
a plurality of first gate electrodes arranged within a first column over the substrate;
a plurality of first doped structures arranged in an alternating arrangement configuration of a first doped structure and a first gate electrode within the first column;
a plurality of second gate electrodes arranged within a second column over the substrate, the second column is adjacent to the first column;
a plurality of second doped structures arranged in an alternating arrangement configuration of a second doped structure and a second gate electrode within the second column; and
an isolation structure in a third column separating the first column from the second column, wherein the isolation structure is laterally in direct contact with the plurality of first gate electrodes and the plurality of first doped structures in the first column, and with the plurality of second gate electrodes and the plurality of second doped structures in the second column, and the isolation structure extends into the substrate.
11 . The semiconductor device of claim 10 , further comprising:
a first contact structure over each first gate electrode of the plurality of first gate electrodes, each first contact structure having a first upper surface; and
a second contact structure over each second gate electrode of the plurality of second gate electrodes, each second contact structure having a second upper surface, and the second upper surface is substantially coplanar with the first upper surface.
12 . The semiconductor device of claim 11 , further comprising:
a third contact structure in the isolation structure, the third contact structure having a third upper surface, and the third upper surface is substantially coplanar with the first upper surface and the second upper surface.
13 . The semiconductor device of claim 10 , wherein the substrate comprises:
a bulk layer;
a buried insulator layer over the bulk layer; and
a semiconductor layer over the buried insulator layer, and the isolation structure terminates within the bulk layer of the substrate.
14 . A method of forming a semiconductor device, comprising:
forming a first gate electrode and a second gate electrode over a substrate, the second gate electrode is laterally adjacent to the first gate electrode, wherein the substrate includes:
a bulk layer;
a buried insulator layer over the bulk layer; and
a semiconductor layer over the buried insulator layer; and
forming an isolation structure between the first gate electrode and the second gate electrode, the isolation structure extends into the substrate and is in direct contact with the first gate electrode and the second gate electrode at laterally adjacent sides thereof, wherein the isolation structure terminates within the bulk layer of the substrate.
15 . The method of claim 14 , wherein forming the first gate electrode and the second gate electrode comprises:
depositing a layer of gate electrode material over the substrate; and
forming a trench through the layer of gate electrode material to a level within the substrate, exposing side surfaces of the first gate electrode and the second gate electrode in the trench.
16 . The method of claim 15 , wherein forming the trench further comprising:
extending the trench through a semiconductor layer and a buried insulator layer of the substrate, the buried insulator layer is under the semiconductor layer, wherein the trench terminates within a bulk layer that is under the buried insulator layer, and at least side surfaces of the semiconductor layer and the buried insulator layer are exposed in the trench.
17 . The method of claim 15 , further comprising:
depositing a first dielectric material to partially fill the trench, the first dielectric material is conformal to the trench;
depositing a second dielectric material to at least fill the trench, the second dielectric material is different from the first dielectric material; and
performing a planarization process to form the isolation structure in the trench, the isolation structure comprises a dielectric liner formed from the first dielectric material and a dielectric core formed from the second dielectric material, wherein the dielectric liner and the dielectric core have upper dielectric surfaces substantially coplanar with each other.
18 . The method of claim 17 , further comprising:
depositing a dielectric layer over the layer of gate electrode material before forming the trench, the dielectric layer having an upper dielectric surface, and the upper dielectric surfaces of the dielectric liner and the dielectric core are substantially coplanar with the upper dielectric surface of the dielectric layer.
19 . The method of claim 18 , further comprising:
forming a first opening in the dielectric layer over the first gate electrode and a second opening in the dielectric core of the isolation structure; and
filling the first opening and the second opening with a conductive material to form a first contact structure over the first gate electrode and a second contact structure in the isolation structure, respectively.