System and method for latency-aware mapping of quantum circuits to quantum chips
A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.
1. A quantum computing system, comprising:
a quantum processor comprising a plurality of qubits;
a classical computer that generates a quantum circuit by:
selecting at least two qubits of the plurality of qubits to be controlled, via analog conversion units, by inputs from the classical computer that are mapped to corresponding classical bits of the classical computer, wherein the at least two qubits are selected so that the quantum circuit has a latency less than or equal to a threshold latency that is less than or equal to a coherence time of the quantum circuit; and
generating the quantum circuit including the at least two qubits and the corresponding classical bits.
2. The quantum computing system of claim 1 , wherein the latency of the quantum circuit is based on a latency associated with qubit readout from quantum data to classical data of each qubit of the at least two qubits.
3. The quantum computing system of claim 1 , wherein the latency of the quantum circuit is further based on a latency associated with a communication dependency with classical logic processing in the classical computer and a third latency due to relative positions of the analog conversion units in the quantum computing system.
4. The quantum computing system of claim 1 , wherein the latency of the quantum circuit is further based on a latency associated with relative positions of the analog conversion units in the quantum computing system.
5. The quantum computing system of claim 1 , wherein the threshold latency corresponds to a lowest latency obtainable by selecting at least two qubits that are closest to each other so as to reduce a relative position of the analog conversion units associated with the at least two qubits.
6. The quantum computing system of claim 1 , wherein the corresponding classical bits are further associated with a specific qubit of the plurality of qubits that will be conditionally controlled.
7. The quantum computing system of claim 1 , wherein each qubit of the plurality of qubits is associated with a different analog conversion unit of the analog conversion units of the quantum computing system.
8. A method, comprising:
mapping, by a classical computer of a quantum computing system, a group of qubits from a plurality of qubits of a quantum processor to classical bits of the classical computer; and
generating, by the classical computer, a quantum circuit of the quantum processor by:
selecting at least two qubits of the plurality of qubits to be controlled, via analog conversion units, by inputs from the classical computer that are mapped to corresponding classical bits of the classical computer, wherein the at least two qubits are selected so that the quantum circuit has a latency less than or equal to a threshold latency that is less than or equal to a coherence time of the quantum circuit; and
generating the quantum circuit including the at least two qubits and the corresponding classical bits.
9. The method of claim 8 , wherein the latency of the quantum circuit is based on a latency associated with qubit readout from quantum data to classical data of each qubit of the at least two qubits.
10. The method of claim 8 , wherein the latency of the quantum circuit is further based on a latency associated with a communication dependency with classical logic processing in the classical computer and a third latency due to relative positions of the analog conversion units in the quantum computing system.
11. The method of claim 8 , wherein the latency of the quantum circuit is further based on a latency associated with relative positions of the analog conversion units in the quantum computing system.
12. The method of claim 8 , wherein the threshold latency corresponds to a lowest latency obtainable by selecting at least two qubits that are closest to each other so as to reduce a relative position of the analog conversion units associated with the at least two qubits.
13. The method of claim 8 , wherein the corresponding classical bits are associated with a specific qubit of the plurality of qubits that will be conditionally controlled.
14. The method of claim 8 , wherein each qubit of the plurality of qubits is associated with a different analog conversion unit of the analog conversion units of the quantum computing system.
15. A computer readable medium on which is stored non-transitory computer-executable code, which when executed by a classical computer of a quantum computing system, causes the classical computer to:
map a group of qubits from a plurality of qubits of a quantum processor to classical bits of the classical computer; and
generate a quantum circuit of the quantum processor by:
selecting at least two qubits of the plurality of qubits to be controlled, via analog conversion units, by inputs from the classical computer that are mapped to corresponding classical bits of the classical computer, wherein the at least two qubits are selected so that the quantum circuit has a latency less than or equal to a threshold latency that is less than or equal to a coherence time of the quantum circuit; and
generating the quantum circuit including the at least two qubits and the corresponding classical bits.
16. The computer readable medium according to claim 15 , wherein the latency of the quantum circuit is based on a latency associated with qubit readout from quantum data to classical data of each qubit of the at least two qubits.
17. The computer readable medium according to claim 15 , wherein the latency of the quantum circuit is further based on a latency associated with a communication dependency with classical logic processing in the classical computer and a third latency due to relative positions of the analog conversion units in the quantum computing system.
18. The computer readable medium according to claim 15 , wherein the latency of the quantum circuit is further based on a latency associated with relative positions of the analog conversion units in the quantum computing system.
19. The computer readable medium according to claim 15 , wherein the threshold latency corresponds to a lowest latency obtainable by selecting at least two qubits that are closest to each other so as to reduce a relative position of the analog conversion units associated with the at least two qubits.
20. The computer readable medium according to claim 15 , wherein the corresponding classical bits are associated with a specific qubit of the plurality of qubits that will be conditionally controlled.