Low-dropout voltage regulator with split-buffer stage
Techniques are described herein for regulating output voltage using a low-dropout (LDO) voltage regulator. In an example, an LDO voltage regulator circuit includes a pass circuit that is driven or otherwise controlled by a first buffer circuit, and a sense circuit that is driven or otherwise controlled by a second buffer circuit. The pass circuit is configured to pass current from a voltage supply terminal to an output voltage terminal, responsive to a first control signal. The sense circuit is configured to sense the current passed by the pass circuit, responsive to a second control signal. The first buffer circuit is configured to provide the first control signal to the pass circuit, responsive to a third control signal, and the second buffer circuit is configured to provide the second control signal to the pass circuit, also responsive to the third control signal.
1. A circuit, comprising:
a pass circuit coupled to a voltage supply terminal and having a pass circuit control terminal and a pass circuit output;
a sense circuit coupled to the voltage supply terminal and having a sense circuit control terminal, wherein the sense circuit is coupled to the pass circuit output;
a first buffer circuit having a first buffer input and a first buffer output, the first buffer input coupled to a control voltage terminal, and the first buffer output coupled to the pass circuit control terminal, wherein the first buffer circuit includes a first buffer circuit transistor having a control terminal coupled to the control voltage terminal, a first current terminal coupled to the voltage supply terminal, and a second current terminal coupled to the pass circuit control terminal, a first current source, and a current mirror coupled in parallel with the first current source; and
a second buffer circuit having a second buffer input and a second buffer output, the second buffer input coupled to the control voltage terminal, and the second buffer output coupled to the sense circuit control terminal.
2. The circuit of claim 1 , comprising:
an error amplifier circuit having a first input, a second input, and an error amplifier output, wherein the pass circuit is coupled between the voltage supply terminal and the first input of a comparator circuit, and the sense circuit is coupled between the voltage supply terminal and the second input of the comparator circuit.
3. The circuit of claim 2 , wherein the error amplifier circuit comprises:
a second current source;
a third current source;
a first field effect transistor (FET) having one of its source or drain coupled to the sense circuit and the other of its source or drain coupled to the first current source; and
a second FET having its gate coupled to the gate of the first FET and the first current source, one of its source or drain coupled to the pass circuit, and the other of its source or drain coupled to the second current source.
4. The circuit of claim 3 , comprising:
a third FET having its gate coupled to the second current source, one of its source or drain coupled to the sense circuit, and the other of its source or drain coupled to the current mirror.
5. The circuit of claim 1 , comprising:
a capacitor coupled between the voltage supply terminal and the control voltage terminal; and
a resistor coupled between the voltage supply terminal and the control voltage terminal.
6. The circuit of claim 1 , wherein:
the first buffer circuit transistor is a first field effect transistor (FET); and
the second buffer circuit includes a second FET and a second current source, the second FET having its gate coupled to the control voltage terminal, its drain coupled to the voltage supply terminal, and its source coupled to the second current source and the sense circuit control terminal.
7. The circuit of claim 1 , wherein the pass circuit is coupled between the voltage supply terminal and an output voltage terminal, the circuit comprising:
a control circuit coupled to the output voltage terminal and having a voltage reference input.
8. A system comprising:
the circuit of claim 1 ;
a power supply coupled to the voltage supply terminal of the circuit; and
a load coupled to an output voltage terminal of the circuit.
9. A low-dropout (LDO) voltage regulator circuit, comprising:
a pass circuit configured to pass current from a voltage supply terminal to an output voltage terminal, responsive to a first control signal, wherein the pass circuit includes a pass circuit control terminal and a pass circuit output;
a sense circuit configured to sense the current passed by the pass circuit, responsive to a second control signal, wherein the sense circuit is coupled to the pass circuit output;
a first buffer circuit configured to provide the first control signal, responsive to a third control signal, wherein the first buffer circuit includes a first buffer circuit transistor having a control terminal coupled to a control voltage terminal, a first current terminal coupled to the voltage supply terminal, and a second current terminal coupled to the pass circuit control terminal, a first current source, and a current mirror coupled in parallel with the first current source; and
a second buffer circuit configured to provide the second control signal, responsive to the third control signal.
10. The LDO voltage regulator circuit of claim 9 , comprising:
an error amplifier circuit configured to compare an output potential of the sense circuit with an output potential of the pass circuit.
11. The LDO voltage regulator circuit of claim 10 , wherein the error amplifier circuit comprises:
a first current source;
a second current source;
a first field effect transistor (FET) having one of its source or drain configured to receive the output potential of the sense circuit and the other of its source or drain coupled to the first current source; and
a second FET having its gate coupled to the first current source and the gate of the first FET, one of its source or drain configured to receive the output potential of the pass circuit, and the other of its source or drain coupled to the second current source.
12. The LDO voltage regulator circuit of claim 11 , comprising:
a current mirror circuit configured to fold an output current of the sense circuit into an output current of the first buffer circuit, to adaptively control the first control signal; and
a third FET configured to reduce difference between the output potential of the sense circuit and the output potential of the pass circuit.
13. The LDO voltage regulator circuit of claim 9 , comprising:
a current source;
a first field effect transistor (FET) having its source or drain coupled to the current source and configured to convert potential variations at the output voltage terminal to feedback current, responsive to a voltage reference signal at a gate of the FET; and
a second FET having its gate configured to receive a fourth control signal, one of its source or drain coupled to a control terminal of the second buffer circuit that receives the third control signal, and the other of its source or drain coupled to the current source.
14. A system comprising:
the LDO voltage regulator circuit of claim 9 ;
a power supply coupled to the voltage supply terminal of the LDO voltage regulator circuit; and
a load coupled to an output voltage terminal of the LDO voltage regulator circuit.
15. A voltage regulation method using a low-dropout (LDO) voltage regulator circuit, the method comprising:
passing, via a pass element, current from a voltage supply terminal to an output voltage terminal, responsive to a first control signal, wherein the pass element includes a pass element control terminal and a pass element output;
sensing, via a sense element, the current passed by the pass element, responsive to a second control signal, wherein the sense element is coupled to the pass element output;
responsive to a third control signal, providing, via a first buffer circuit, the first control signal, wherein the first buffer circuit includes a first buffer circuit transistor having a control terminal coupled to a control voltage terminal, a first current terminal coupled to the voltage supply terminal, and a second current terminal coupled to the pass element control terminal, a first current source, and a current mirror coupled in parallel with the first current source; and
responsive to the third control signal, providing, via a second buffer circuit, the second control signal.
16. The method of claim 15 , comprising:
comparing, via an error amplifier circuit, an output potential of the sense element with an output potential of the pass element.
17. The method of claim 16 , comprising:
reducing, via a transistor, difference between the output potential of the sense element and the output potential of the pass element.
18. The method of claim 15 , comprising:
adding, via a current mirror circuit, output current of the sense element into output current of the first buffer circuit, to adaptively adjust the first control signal.
19. The method of claim 15 , comprising:
responsive to a voltage reference signal, converting potential variations at the output voltage terminal to feedback current.