IMPROVED SEALS FOR SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODE PIXELS
A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.
1 . A semiconductor device having a frontside and a backside, comprising:
a substrate at the backside;
dielectric layers on the substrate;
first and second metal layers interleaved with the dielectric layers;
a through silicon via formed in the backside through the substrate and the dielectric layers;
a first through silicon via seal ring that extends between the substrate and the first metal layer; and
a second through silicon via seal ring that extends between the first metal layer and the second metal layer.
2 . The semiconductor device of claim 1 , wherein the first through silicon via seal ring contacts a first portion of the first metal layer, and the second through silicon via seal ring contacts a second portion of the first metal layer that is offset from the first portion.
3 . The semiconductor device of claim 2 , further comprising:
a die seal having a first portion that extends from the substrate to the first metal layer and a second portion that extends from the first metal layer to the second metal layer.
4 . The semiconductor device of claim 2 , wherein the second metal layer is a 30V cathode bond pad, and the second through silicon via seal ring contacts the 30V cathode bond pad.
5 . The semiconductor device of claim 2 , wherein the first through silicon via seal ring and the second through silicon via seal ring are merged with a die seal at an edge of the substrate.
6 . The semiconductor device of claim 2 , wherein the second through silicon via seal ring contacts a first portion of the second metal layer, the semiconductor device further comprising:
a third metal layer, wherein the second metal layer is interposed between the first metal layer and the third metal layer;
a third through silicon via seal ring that extends between the first portion of the second metal layer and the third metal layer.
7 . The semiconductor device of claim 6 , further comprising:
a fourth through silicon via seal ring that extends from the first portion of the first metal layer to a second portion of the second metal layer that is different from the first portion of the second metal layer.
8 . The semiconductor device of claim 6 , wherein the first through silicon via seal ring, the second through silicon via seal ring, and the third through silicon via seal ring are merged with a die seal at an edge of the substrate.
9 . The semiconductor device of claim 1 , wherein the first through silicon via seal ring contacts a given portion of the first metal layer, and the second through silicon via seal ring contacts the given portion of the first metal layer.
10 . The semiconductor device of claim 9 , further comprising:
a die seal having a first portion that extends from the substrate to the first metal layer and a second portion that extends from the first metal layer to the second metal layer.
11 . The semiconductor device of claim 9 , wherein the first through silicon via seal ring and the second through silicon via seal ring are merged with a die seal at an edge of the substrate.
12 . The semiconductor device of claim 9 , wherein the second through silicon via seal ring contacts a given portion of the second metal layer, the semiconductor device further comprising:
a third metal layer, wherein the second metal layer is interposed between the first metal layer and the third metal layer;
a third through silicon via seal ring that extends between the given portion of the second metal layer and the third metal layer.
13 . The semiconductor device of claim 12 , wherein the second metal layer comprises a 0V anode bond pad, and the second through silicon via seal ring contacts the 0V anode bond pad.
14 . A semiconductor device, comprising:
a substrate;
a first metal layer;
a second metal layer;
a through silicon via that extends through the substrate to the second metal layer; and
first and second through silicon via seal rings, wherein the first through silicon via seal ring extends from the substrate to a first portion of the first metal layer, and the second through silicon via seal ring extends from the second metal layer to a second portion of the first metal layer that is offset from the first portion.
15 . The semiconductor device of claim 14 , wherein the second metal layer comprises a 30V cathode bond pad, and wherein the second through silicon via seal ring is coupled to the 30V cathode bond pad.
16 . The semiconductor device of claim 15 , further comprising:
a barrier layer that extends between the first portion of the first metal layer and the second portion of the first metal layer to cover the offset.
17 . The semiconductor device of claim 15 , further comprising:
a die seal having a first portion that extends from the substrate to the first metal layer and a second portion that extends from the first metal layer to the second metal layer.
18 . The semiconductor device of claim 15 , wherein the first and second through silicon via seal rings are merged with a die seal at an edge of the substrate.
19 . A semiconductor device, comprising:
a substrate;
a first metal layer;
a second metal layer;
a through silicon via that extends through the substrate to the second metal layer; and
first and second through silicon via seal rings, wherein the first through silicon via seal ring extends from the substrate to a given portion of the first metal layer, the second through silicon via seal ring extends from the given portion of the first metal layer to the second metal layer, and the first and second through silicon via seal rings are merged with a die seal at an edge of the substrate.
20 . The semiconductor device of claim 19 , wherein the second metal layer comprises a 0V anode bond pad, and wherein the second through silicon via seal ring is coupled to the 0V anode bond pad.