Granted Patent B2

US 12,407,425 · App. 18/052,522 · Granted Sep 2, 2025

Inventor: Rainer Evers (Hamburg, DE)

Assignee: NXP B.V.

H04B15/02H04B1/40H04B3/02

Abstract

Claims (26)

1. An interference suppression module for an Ethernet transceiver, the interference suppression module comprising circuitry configured to:

receive a receiver output from a receiver module of the Ethernet transceiver, the receiver module configured to output a logic-high when a received voltage signal is higher than a receiver threshold, and output a logic-low when the received voltage signal is lower than the receiver threshold;

receive an energy detection output from an energy detection module of the Ethernet transceiver, the energy detection module configured to output a logic-high when the received voltage signal is higher than a positive energy detection threshold or lower than a negative energy detection threshold, and output a logic-low when the received voltage signal is between the positive and negative energy detection thresholds; and

output a predefined logic state to a receive pin of the Ethernet transceiver when the energy detection output is a logic-low.

2. The interference suppression module of claim 1 , wherein the circuitry comprises an AND gate configured to receive the receiver output from the receiver module and the energy detection output from the energy detection module and output a logic-low to the receive pin when the energy detection output is a logic-low.

3. The interference suppression module of claim 1 , wherein the circuitry comprises a NAND gate configured to receive the receiver output from the receiver module and the energy detection output from the energy detection module and output a logic-high to the receive pin when the energy detection output is a logic-low.

4. The interference suppression module of claim 1 , wherein the circuitry is configured to output the predefined logic state to the receive pin when the energy detection output is a logic-low for a predefined time.

5. The interference suppression module of claim 2 , wherein the circuitry comprises a time-delay unit configured to receive the energy detection output from the energy detection module and, when the energy detection output is a logic-low for a predefined time, pass the energy detection output to the AND gate.

6. The interference suppression module of claim 3 , wherein the circuitry comprises a time-delay unit configured to receive the energy detection output from the energy detection module and, when the energy detection output is a logic-low for a predefined time, pass the energy detection output to the NAND gate.

7. The interference suppression module of claim 1 , wherein the circuitry is configured to pass the receiver output to the receive pin when the energy detection output is a logic-high.

8. The interference suppression module of claim 1 , wherein the circuitry is configured to output the energy detection output to an energy detection pin of the Ethernet transceiver.

9. The interference suppression module of claim 8 , wherein the circuitry comprises a time-delay unit configured to receive the energy detection output from the energy detection module and, when the energy detection output is a logic-low for a predefined time, pass the energy detection output to the energy detection pin.

10. An Ethernet transceiver comprising the interference suppression module of claim 1 .

11. The Ethernet transceiver of claim 10 , wherein the receiver and energy detection modules each comprise one or more comparators for comparing the received voltage signal with the respective thresholds, and one or more low-pass filters configured to remove noise from the outputs of the comparators.

12. The Ethernet transceiver of claim 11 , wherein the energy detection module comprises first and second comparators for comparing the received voltage signal with the respective positive and negative energy detection thresholds, and a XOR gate configured to provide the energy detection output based on the outputs of the first and second comparators.

13. The Ethernet transceiver of claim 10 , wherein the receiver threshold comprises a predefined hysteresis.

14. The Ethernet transceiver of claim 10 , further comprising one or more signal pins connectable to a signal line for receiving the received voltage signal over an Ethernet network.

15. The Ethernet transceiver of claim 14 , wherein the one or more signal pins are configured to be connected to a signal line comprising a single unshielded twisted pair.

16. The Ethernet transceiver of claim 14 , wherein the received voltage signal is a differential voltage signal.

17. The Ethernet transceiver of claim 10 , wherein the Ethernet transceiver is a 10BASE-T1S transceiver.

18. An Ethernet Physical Layer comprising the Ethernet transceiver of claim 10 .

19. A method of interference suppression in an Ethernet transceiver, the method comprising:

receiving a receiver output from a receiver module of the Ethernet transceiver, the receiver module configured to output a logic-high when a received voltage signal is higher than a receiver threshold, and output a logic-low when the received voltage signal is lower than the receiver threshold;

receiving an energy detection output from an energy detection module of the Ethernet transceiver, the energy detection module configured to output a logic-high when the received voltage signal is higher than a positive energy detection threshold or lower than a negative energy detection threshold, and output a logic-low when the received voltage signal is between the positive and negative energy detection thresholds; and

outputting a predefined logic state to a receive pin of the Ethernet transceiver when the energy detection output is a logic-low.

20. A non-transitory computer-readable medium storing instructions that, when executed by a computer, cause it to perform the method of claim 19 .

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (11)