Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN)

1. A method of operating a power module having a bi-directional double-base bipolar junction transistor, the method comprising:

conducting a first load current from an upper terminal of the power module, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal

interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead of the transistor to the lower terminal; and

blocking current from the upper terminal to the lower terminal by the transistor.

2. The method of claim 1 :

wherein interrupting the first load current further comprises interrupting the first load current with the lower-main FET having a breakdown voltage of 100 Volts or less; and

wherein blocking current further comprises blocking at an applied voltage across the upper terminal and the lower terminal of 600 Volts or greater.

3. The method of claim 1 further comprising, after blocking current from the upper terminal to the lower terminal:

conducting a second load current from the lower terminal of the power module, through the transistor, and from an upper-main lead of the transistor to the upper terminal; and then responsive to assertion of a second interrupt signal

interrupting the second load current from the upper-main lead to the upper terminal by opening an upper-main FET and commutating a second shutoff current through an upper-control lead of the transistor to the upper terminal; and

blocking current from the lower terminal to the upper terminal by the transistor.

4. The method of claim 3 :

wherein interrupting the second load current further comprises interrupting the second load current with the upper-main FET having a breakdown voltage of 100 Volts or less; and

wherein blocking current from the lower terminal to the upper terminal further comprises blocking at an applied voltage across the lower terminal and the upper terminal of 600 Volts or greater.

5. The method of claim 1 transistor is at least one selected from a group comprising: a NPN transistor; and a PNP transistor.

6. A switch assembly comprising:

an upper terminal, a lower terminal, and an upper-control input;

a transistor defining an upper-control lead, an upper-main lead, a lower-control lead, and a lower-main lead;

an upper-main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper-main lead, and a gate;

a lower-main FET defining a first lead coupled to the lower-main lead, a second lead coupled to the lower terminal, and a gate;

a controller coupled to the upper-control input, the gate of the upper-main FET, and the gate of the lower-main FET, and for a first applied voltage across the upper terminal and the lower terminal, the controller configured to:

assert the gate of the upper-main FET to make the upper-main FET conductive, arrange the transistor for conduction, and assert the gate of the lower-main FET to make the lower-main FET conductive such that a first load current flows from the upper terminal to the lower terminal;

sense de-assertion of the upper-control input; and responsive to de-assertion of the upper-control input

de-assert the gate of the lower-main FET to interrupt the first load current and commutate a first shutoff current through the lower-control lead to the lower terminal; and

arrange the transistor to block current flow from the upper terminal to the lower terminal.

7. The switch assembly of claim 6 wherein the breakdown voltage of the transistor is 600 Volts or greater, and the breakdown voltage of the lower-main FET is 100 Volts or less.

8. The switch assembly of claim 6 wherein the breakdown voltage of the transistor is about 1200 Volts, and the breakdown voltage of the lower-main FET is 80 Volts or less.

9. The switch assembly of claim 6 further comprising:

an upper-control FET having a first lead coupled to the upper-control lead, a second lead coupled to the upper terminal, and a gate, and during periods when the first load current flows from the upper terminal to the lower terminal, the upper-control FET is conductive; and

wherein when the controller arranges the transistor to block current flow from the upper terminal to the lower terminal, the controller is further configured to de-assert the gate of the upper-control FET to electrically float the upper-control lead.

10. The switch assembly of claim 6 further comprising:

a lower-control input coupled to the controller; and

wherein for a second applied voltage across the upper terminal and lower terminal, the second applied voltage having a polarity opposite the first applied voltage, the controller is further configured to:

assert the gate of the lower-main FET to make the lower-main FET conductive, arrange the transistor for conduction, and assert the gate of the upper-main FET to make the upper-main FET conductive such that a second load current flows from the lower terminal to the upper terminal;

sense de-assertion of the lower-control input; and responsive to de-assertion of the lower-control input

de-assert the gate of the upper-main FET to interrupt the second load current and commutate a second shutoff current through the upper-control lead to the upper terminal; and

arrange the transistor to block current flow from the lower terminal to the upper terminal.

11. The switch assembly of claim 10 further comprising:

a lower-control FET having a first lead coupled to the lower-control lead, a second lead coupled to the lower terminal, and a gate, and during periods when the second load current flows from the upper terminal to the lower terminal, the lower-control FET is conductive; and

wherein when the controller arranges the transistor to block current flow from the lower terminal the upper terminal, the controller is further configured to de-assert the gate of the lower-control FET to electrically float the lower-control lead of the transistor.

12. The switch assembly of claim 10 wherein the breakdown voltage of the transistor is 600 Volts or greater, and the breakdown voltage of the lower-main FET is 100 Volts or less.

13. The switch assembly of claim 6 wherein the transistor is at least one selected from a group comprising: a NPN transistor; and a PNP transistor.

14. A method of operating a bi-directional double-base bipolar junction transistor, the method comprising:

making the transistor conductive from an upper-main lead to a lower-main lead by supplying current to an upper-control lead of the transistor and electrically floating a lower-control lead of the transistor; and then

making the transistor non-conductive by electrically floating the upper-control lead, electrically floating the lower-main lead, and conducting a shutoff current through the lower-control lead.

15. The method of claim 14 wherein electrically floating the lower-main lead further comprises making non-conductive a lower-main electrically-controlled switch coupled to the lower-main lead of the transistor.

16. The method of claim 14 wherein making the transistor conductive further comprises:

closing an upper-main electrically-controlled switch coupled between an upper terminal and the upper-main lead; and

closing a lower-main electrically-controlled switch coupled between a lower terminal and the lower-main lead.

17. The method of claim 16 wherein making the transistor non-conductive further comprises:

opening the upper-main electrically-controlled switch;

conducting the shutoff current to the upper-main lead through a diode associated with the upper-main electrically-controlled switch; and

commutating the shutoff current through the lower-control lead by opening the lower-main electrically-controlled switch.

18. The method of claim 14 wherein conducting the shutoff current through the lower-control lead further comprises conducting current through a diode associated with an electrically-controlled switch coupled to the lower-control lead.

19. The method of claim 14 wherein supplying current to the upper-control lead further comprises at least one selected from a group comprising: supplying current at a voltage about the same as a voltage applied to the upper-main lead; and supplying current at a voltage higher than a voltage applied at the upper-main lead.

20. The method of claim 14 wherein the transistor is at least one selected from a group comprising: a NPN transistor; and a PNP transistor.