Backside programmable gate array
Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.
1 . A method for forming a semiconductor device, the method comprising:
forming a front end of line structure comprising an array of transistors, each transistor of the array of transistors comprising one or more backside vias in direct contact with a source/drain region of the respective transistor and one or more backside vias in direct contact with a gate of the respective transistor, wherein a first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias;
forming a back end of line structure on a first surface of the front end of line structure; and
forming a backside structure on a second surface of the front end of line structure opposite the first surface, the backside structure comprising a backside metallization layer in direct contact with the one or more programmed backside vias.
2 . The method of claim 1 , wherein the backside structure comprises a backside power delivery network.
3 . The method of claim 1 , wherein the one or more placeholder backside vias comprise a dielectric material and the one or more programmed backside vias comprise a conductive material.
4 . The method of claim 3 , wherein the backside metallization layer is in direct contact with the one or more backside vias.
5 . The method of claim 1 , wherein the one or more placeholder backside vias and the one or more programmed backside vias comprise a conductive material.
6 . The method of claim 5 , further comprising, for each of the one or more programmed backside vias, a backside extension via between the backside metallization layer and the respective programmed backside via.
7 . The method of claim 5 , wherein the backside metallization layer is patterned to prevent direct contact with the one or more placeholder backside vias.
8 . The method of claim 5 , wherein the one or more placeholder backside vias are recessed with respect to the one or more programmed backside vias to prevent direct contact with the backside metallization layer.
9 . The method of claim 1 , wherein the one or more programmed backside vias are selected such that a portion of the array of transistors defines a logic functional circuit.
10 . A semiconductor device comprising:
a front end of line structure comprising an array of transistors, each transistor of the array of transistors comprising one or more backside vias in direct contact with a source/drain region of the respective transistor and one or more backside vias in direct contact with a gate of the respective transistor, wherein a first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias;
a back end of line structure on a first surface of the front end of line structure; and
a backside structure on a second surface of the front end of line structure opposite the first surface, the backside structure comprising a backside metallization layer in direct contact with the one or more programmed backside vias.
11 . The semiconductor device of claim 10 , wherein the backside structure comprises a backside power delivery network.
12 . The semiconductor device of claim 10 , wherein the one or more placeholder backside vias comprise a dielectric material and the one or more programmed backside vias comprise a conductive material.
13 . The semiconductor device of claim 12 , wherein the backside metallization layer is in direct contact with the one or more backside vias.
14 . The semiconductor device of claim 10 , wherein the one or more placeholder backside vias and the one or more programmed backside vias comprise a conductive material.
15 . The semiconductor device of claim 14 , further comprising, for each of the one or more programmed backside vias, a backside extension via between the backside metallization layer and the respective programmed backside via.
16 . The semiconductor device of claim 14 , wherein the backside metallization layer is patterned to prevent direct contact with the one or more placeholder backside vias.
17 . The semiconductor device of claim 14 , wherein the one or more placeholder backside vias are recessed with respect to the one or more programmed backside vias to prevent direct contact with the backside metallization layer.