IP Library Granted Patent US 12,490,481
Granted Patent B2
US 12,490,481 · App. 18/056,736 · Granted Dec 2, 2025

Semiconductor devices and methods for fabricating the same

Inventors: Bong Kwan Baek (Suwon-si, KR); Jun Hyuk Lim (Suwon-si, KR); Jung Hwan Chun (Suwon-si, KR); Kyu-Hee Han (Suwon-si, KR); Jong Min Baek (Suwon-si, KR); Koung Min Ryu (Suwon-si, KR); Jung Hoo Shin (Suwon-si, KR); Sang Shin Jang (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D62/121H10D30/47H10D30/6729H10D30/6757
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,490,481
App. No.
18/056,736
Granted
Dec 2, 2025
Kind
B2
Abstract

Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern extending in a first direction, gate structures spaced apart from each other in the first direction on the active pattern, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner extending along a sidewall of the source/drain contacts. A carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

Claims (42)

1 . A semiconductor device comprising:

an active pattern extending in a first direction;

a plurality of gate structures spaced apart from each other in the first direction on the active pattern and including a first gate structure that includes a gate electrode and a gate spacer, the gate electrode extending in a second direction;

a source/drain pattern on the active pattern;

a source/drain contact on the source/drain pattern; and

a contact liner extending along a sidewall of the source/drain contact,

wherein a carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height,

wherein the carbon concentration of the contact liner at the first point of the contact liner is lower than the carbon concentration of the contact liner at the second point of the contact liner.

2 . The semiconductor device of claim 1 , wherein a thickness of the contact liner at the first height is smaller than a thickness of the contact liner at the second height.

3 . The semiconductor device of claim 1 , wherein a thickness of the contact liner at the first height is equal to a thickness of the contact liner at the second height.

4 . The semiconductor device of claim 1 , further comprising an etching stop layer extending along a sidewall of the first gate structure and an upper surface of the source/drain pattern,

wherein the contact liner does not extend through the etching stop layer.

5 . The semiconductor device of claim 1 , further comprising a contact silicide layer that is between the source/drain contact and the source/drain pattern,

wherein the contact liner is in contact with the contact silicide layer.

6 . The semiconductor device of claim 1 , wherein the contact liner comprises an insulating material that includes oxygen.

7 . The semiconductor device of claim 6 , wherein a ratio of carbon to oxygen of the contact liner at the first point is smaller than a ratio of carbon to oxygen of the contact liner at the second point.

8 . The semiconductor device of claim 1 , wherein the contact liner extends up to an upper surface of the first gate structure.

9 . The semiconductor device of claim 1 , wherein the contact liner is in contact with the source/drain contact.

10 . The semiconductor device of claim 1 , wherein the active pattern includes a lower pattern and a plurality of sheet patterns spaced apart from the lower pattern in a third direction that is perpendicular to the first direction and the second direction, and the gate electrode surrounds the plurality of sheet patterns.

11 . A semiconductor device comprising: an active pattern extending in a first direction;

a field insulating layer on a sidewall of the active pattern;

a plurality of gate structures spaced apart from each other in the first direction on the active pattern, each of the plurality of gate structures including a gate electrode, and the gate electrode extending in a second direction;

a source/drain pattern on the active pattern;

an etching stop layer extending along an upper surface of the field insulating layer and a surface of the source/drain pattern;

an interlayer insulating layer on the etching stop layer;

a source/drain contact in the interlayer insulating layer and connected to the source/drain pattern; and

a contact liner between the source/drain contact and the interlayer insulating layer, wherein a ratio of carbon to oxygen at a first point of the contact liner is smaller than a ratio of carbon to oxygen at a second point of the contact liner, and

the first point is at a first height from a bottom surface of the source/drain pattern, the second point is at a second height from the bottom surface of the source/drain pattern, and the first height is smaller than the second height.

12 . The semiconductor device of claim 11 , wherein a thickness of the contact liner at the first height is smaller than a thickness of the contact liner at the second height.

13 . The semiconductor device of claim 11 , wherein a thickness of the contact liner at the first height is equal to a thickness of the contact liner at the second height.

14 . The semiconductor device of claim 11 , wherein the contact liner is on the etching stop layer, and

a lowermost portion of the contact liner is in contact with the etching stop layer.

15 . The semiconductor device of claim 11 , further comprising a contact silicide layer that is between the source/drain contact and the source/drain pattern, wherein the contact liner is in contact with the contact silicide layer.

16 . The semiconductor device of claim 11 , wherein the contact liner includes SiOC.

17 . A semiconductor device comprising:

an active pattern including a lower pattern extending in a first direction and a sheet pattern spaced apart from the lower pattern in a second direction;

a plurality of gate structures spaced apart from each other in the first direction on the lower pattern, each of the plurality of gate structures including a gate electrode and a gate spacer, and the gate electrode extending in a third direction;

a source/drain pattern on the lower pattern and in contact with the sheet pattern; a source/drain contact on the source/drain pattern;

a contact silicide layer between the source/drain pattern and the source/drain contact;

and a contact liner extending along a sidewall of the source/drain contact and including SiOC, wherein a carbon concentration of the contact liner at a first point of the contact liner is lower than a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

18 . The semiconductor device of claim 17 , wherein a thickness of the contact liner at the first height is smaller than a thickness of the contact liner at the second height.

19 . The semiconductor device of claim 17 , wherein the contact liner is not in contact with the contact silicide layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2022
From: BAEK, BONG KWAN; LIM, JUN HYUK; CHUN, JUNG HWAN; HAN, KYU-HEE; BAEK, JONG MIN; RYU, KOUNG MIN; SHIN, JUNG HOO; JANG, SANG SHIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061818/0693 →
Priority Claims (1)
KR 10-2022-0045199 · Apr 12, 2022 · national
Continuity (1)
Related Publication 20230326964A1 · Oct 12, 2023
References Cited (15)
US 10283406B2 · Basker et al. · 2019 [cited by applicant]
US 10672773B2 · Ji et al. · 2020 [cited by applicant]
US 10950434B2 · Jhan et al. · 2021 [cited by applicant]
US 10971589B2 · Kao et al. · 2021 [cited by applicant]
US 11121234B2 · Liaw · 2021 [cited by applicant]
US 20130049219A1 · Tsai et al. · 2013 [cited by applicant]
US 20160141381A1 · Kim et al. · 2016 [cited by applicant]
US 20170222014A1 · Tak · 2017 [cited by examiner]
US 20200027719A1 · Liao et al. · 2020 [cited by applicant]
US 20210066453A1 · Lee · 2021 [cited by examiner]
US 20210184018A1 · Khaderbad · 2021 [cited by examiner]
US 20210407808A1 · Chou · 2021 [cited by examiner]
US 20210408262A1 · Liaw · 2021 [cited by applicant]
European Office Action corresponding to EP Application No. 23155297.7; dated Sep. 20, 2023 (8 pages). [cited by applicant]
European Search Report corresponding to EP Application No. 23155297.7; dated Sep. 8, 2023 (4 pages). [cited by applicant]