Forksheet field effect transistor including self-aligned gate
A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.
1 . A method of fabrication a semiconductor device, the method comprising:
forming a stack of semiconductor nanosheets on a semiconductor substrate;
performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin, the first and second nanosheet fins separated by one another by a distance defining an isolation region;
forming an isolation wall in the isolation region, the isolation wall extending continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface;
forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall; and
forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.
2 . The method of claim 1 , wherein the wall upper surface is completely beneath the gate ILD.
3 . The method of claim 2 , wherein performing the nanosheet fin reveal cut process comprises:
depositing a lithographic mask on an upper surface of the stack of semiconductor nanosheets;
patterning the lithographic mask to form mask elements which define an opening therebetween that exposes a portion of the underlying stack of semiconductor nanosheets; and
etching the exposed portion of the stack of semiconductor nanosheets until reaching the semiconductor substrate to form the isolation region.
4 . The method of claim 3 , wherein forming the isolation wall comprises:
filling the isolation region with a dielectric material such that the dielectric material reaches an upper surface of the mask elements; and
removing the mask elements while maintaining the dielectric material such that the remaining dielectric material defines the isolation wall.
5 . The method of claim 4 , wherein a height of the isolation wall is defined by a combination of a height of the first and second nanosheets along with the height of the mask elements prior to removing the mask elements.
6 . The method of claim 4 , wherein the isolation wall includes a protrusion that extends above an upper surface of the first and second nanosheet fins.
7 . The method of claim 6 , wherein forming the electrically conductive gate stack comprises:
forming a sacrificial gate stack that covers the first nanosheet stack, the second nanosheet stack, and the protrusion of the isolation wall;
performing a planarization process so that an upper surface of the sacrificial gate stack is co-planar with respect to the wall upper surface; and
performing a replacement metal gate (RMG) process that replaces the sacrificial gate stack with the electrically conductive gate stack.
8 . A method of fabricating a semiconductor device, the method comprising:
forming a stack of semiconductor nanosheets on a semiconductor substrate;
performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin, the first and second nanosheet fins separated by one another by a distance defining an isolation region;
forming an isolation wall in the isolation region, the isolation wall extending continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface;
forming a sacrificial gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall;
etching a portion of the sacrificial gate stack and the isolation wall such a wall upper surface is below an upper surface of the sacrificial gate stack; and
replacing the sacrificial gate stack with an electrically conductive gate stack, the electrically conductive gate stack including a shared gate region between the wall upper surface and an upper surface of the electrically conductive gate.
9 . The method of claim 8 , further comprising forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack.
10 . The method of claim 9 , wherein the etching further comprises:
depositing a hard mask on an upper surface of the sacrificial gate stack and patterning the hard mask to form an opening that exposes a portion of the underlying sacrificial gate;
performing a second etching process that removes a portion of the sacrificial gate stack to form a cavity that exposes the wall upper surface; and
depositing a sacrificial filler material that completely fills the cavity and completely fills the opening.
11 . The method of claim 10 , wherein the etching further comprises:
depositing a hard mask on an upper surface of the sacrificial gate and patterning the hard mask to form an opening that extends into the underlying sacrificial gate stack and exposes the wall upper surface; and
depositing a sacrificial filler material that fills the cavity and the opening.
12 . The method of claim 11 , wherein replacing the sacrificial gate stack with the electrically conductive gate stack forms a gate cavity in the electrically conductive gate defined by the opening that extends into the previously sacrificial gate stack.
13 . The method of claim 12 , wherein forming a gate ILD includes deposing an ILD material on an upper surface the electrically conductive gate stack that fills the gate cavity to form an ILD protrusion that extends into the electrically conductive gate stack, and wherein the shared gate region between the wall upper surface and the ILD protrusion.
14 . The method of claim 13 , wherein the etching further comprises:
depositing a hard mask on an upper surface of the sacrificial gate stack and patterning the hard mask to form an opening that exposes a portion of the underlying sacrificial gate stack;
performing a second etching process that removes a portion of the sacrificial gate stack to form a cavity that exposes the wall upper surface; and
depositing a sacrificial filler material that completely fills the cavity and partially fills the opening.
15 . The method of claim 14 , wherein replacing the sacrificial gate stack with the electrically conductive gate stack forms a gate protrusion that extends above the upper surface of the electrically conductive gate stack.
16 . The method of claim 15 , wherein forming the gate ILD includes deposing an ILD material on the upper surface the electrically conductive gate stack such that the gate protrusion extends into the gate ILD.
17 . A semiconductor device comprising:
a first stack of nanosheet channels on a semiconductor substrate and a second stack of nanosheet channels on the semiconductor substrate;
an isolation wall interposed between the first stack of nanosheet channels and the second stack of nanosheet channels, the isolation wall separating the first and second stacks of nanosheet channels and extending continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface;
an electrically conductive gate stack that surrounds the first stack of nanosheet channels, the second stack of nanosheet channels, and the isolation wall; and
a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack and contacting the wall upper surface of the isolation wall.
18 . The semiconductor device of claim 17 , wherein the wall upper surface is completely beneath the gate ILD.
19 . The semiconductor device of claim 18 , wherein the isolation wall includes a protrusion that extends above an upper surface of the first and second stacks of nanosheet channels.
20 . The semiconductor device of claim 19 , wherein the wall upper surface is coplanar with the upper surface the electrically conductive gate stack.