Integrated voltage regulator and passive components
It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.
1. A method of making a semiconductor package, the method comprising:
providing a first die substrate having formed thereon a first circuit, the first circuit comprising a first portion of a passive component, the passive component selected from the group consisting of: a capacitor, an inductor, a resistor, a fuse, and an antifuse;
providing a second die substrate having formed thereon a second circuit, the second circuit comprising a second portion of the passive component; and
coupling the first portion of the passive component to the second portion of the passive component to complete the passive component functionally coupled to one or both of the first circuit and the second circuit.
2. The method of claim 1 , further comprising:
coupling the first circuit to the second circuit via a hybrid direct bonding technology.
3. The method of claim 1 , wherein the first circuit comprises a voltage regulator circuit comprising at least one active component.
4. The method of claim 1 , further comprising:
mounting the first die substrate or the second die substrate to a first side of a package substrate after the coupling of the first portion of the passive component to the second portion of the passive component.
5. The method of claim 4 , further comprising:
covering the first die substrate, the second die substrate, and at least a portion of the first side of the package substrate with a die seal.
6. The method of claim 4 , further comprising:
mounting a second side of the package substrate to a printed circuit board.
7. The method of claim 1 , further comprising coupling a passive die to the first die, the second die, or both, to complete the passive component or to complete an additional passive component.
8. The method of claim 1 , wherein the passive component comprises a capacitor and the method further comprises:
(i) forming a first conductive plate adjacent a first bonding layer at a surface of the first circuit to form the first portion of the passive component;
(ii) forming a second conductive plate adjacent a second bonding layer at a surface of the second circuit to form the second portion of the passive component; and
(iii) coupling the first bonding layer to the second bonding layer to form an insulator layer coupled between the first conductive plate and the second conductive plate.
9. The method of claim 1 , further comprising:
(i) forming a first bonding layer having a first thickness in a range from 0.1 micrometers to 5.0 micrometers; and
(ii) forming a second bonding layer having a second thickness in a range from 0.1 micrometers to 5.0 micrometers.
10. The method of claim 1 , wherein the passive component comprises an inductor and the method further comprises:
forming a data processing circuit; and
forming an electromagnetic shield between the data processing circuit and the inductor.
11. The method of claim 1 , further comprising:
forming at least a portion of a second passive component in the first circuit, the second passive component selected from the group consisting of: a capacitor, an inductor, a resistor, a fuse, and an antifuse.
12. The method of claim 11 , further comprising:
forming at least a portion of a third passive component in the second circuit, the third passive component selected from the group consisting of: a capacitor, an inductor, a resistor, a fuse, and an antifuse.
13. The method of claim 1 , further comprising:
physically and electrically coupling the first circuit to the second circuit.
14. The method of claim 1 , wherein the first portion of the passive component comprises a metal layer fabricated as part of the first circuit.
15. The method of claim 8 , wherein coupling the first bonding layer to the second bonding layer comprises direct bonding the first bonding layer to the second bonding layer.
16. A method comprising:
forming a package substrate comprising a first side and a second side opposite the first side;
coupling a first side of a first semiconductor die to the second side of the package substrate;
coupling a first bonding layer to a second side of the first semiconductor die opposite the first side of the first semiconductor die;
coupling a second bonding layer to a first side of a second semiconductor die;
forming a circuit comprising at least one active component on the first semiconductor die or the second semiconductor die;
integrating a first portion of a first passive component into the first semiconductor die;
integrating a second portion of the first passive component into the second semiconductor die;
electrically coupling the first portion or the second portion of the first passive component to the circuit; and
completing the first passive component by coupling the second side of the first semiconductor die to the first side of the second semiconductor die.
17. The method of claim 16 , further comprising:
forming a second passive component between the first passive component and the first side of the first semiconductor die, wherein the second passive component is selected from the group consisting of a capacitor, an inductor, and a resistor.
18. The method of claim 16 , further comprising:
forming a second passive component between the first passive component and the second side of the second semiconductor die, wherein the second passive component is selected from the group consisting of: a capacitor, an inductor, and a resistor.
19. The method of claim 16 , wherein coupling the first bonding layer to the second side of the first semiconductor die and the second bonding layer to the first side of the second semiconductor die comprises:
(i) forming the first bonding layer of a thickness in a range from 0.3 micrometers to 2.0 micrometers; and
(ii) forming the second bonding layer of a thickness in a range from 0.3 micrometers to 2.0 micrometers.
20. The method of claim 16 , further comprising:
coupling a die seal to the package substrate and forming an underfill die seal layer between the second side of the package substrate and the first side of the first semiconductor die.
21. A method of forming a semiconductor package, the method comprising:
providing a first semiconductor die having formed thereon a circuit comprising at least one active component;
the first semiconductor die having further formed thereon a first portion of a passive component;
providing a second semiconductor die having formed thereon a second portion of the passive component;
electrically coupling the first portion or the second portion of the passive component to the voltage regulator circuit; and
completing the passive component by electrically coupling the first portion of the passive component to the second portion of the passive component by physically bonding the first semiconductor die to the second semiconductor die.
22. The method of claim 21 , further comprising:
coupling a surface of the physically bonded first semiconductor die and second semiconductor die to a package substrate.