Granted Patent B2

US 12,446,272 · App. 18/058,915 · Granted Oct 14, 2025

Inventors: Jimmy Robert Hannes Franchi (Enköping, SE); Martin Domeij (Sollentuna, SE)

Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

H10D62/109H01L21/0465H10D12/031H10D30/66H10D62/393H10D62/8325

Abstract

Claims (73)

1. A method for manufacturing a semiconductor device, comprising:

providing a body of semiconductor material comprising:

a substrate; and

a semiconductor region over the substrate and comprising a first conductivity type, wherein the semiconductor region comprises a first side of the body of semiconductor and the substrate comprises a second side of the body of semiconductor material opposite to the first side;

providing a first doped region comprising the first conductivity type within the semiconductor region, wherein the first doped region provides a first JFET channel region for a first JFET device;

providing a first mask over the first side comprising a first opening above the first doped region;

providing a second doped region comprising a second conductivity type opposite to the first conductivity type within the first doped region, wherein the second doped region provides a body region for a MOSFET device, a gate region for the first JFET device, and a first JFET gate for a second JFET device;

providing a first spacer structure within the first opening to define a second opening smaller than the first opening;

providing a third doped region comprising the first conductivity type within the second doped region aligned to the second opening, wherein the third doped region provides a second JFET channel region for the second JFET device, a first JFET source for the first JFET device, and a JFET drain for the second JFET device;

providing a second spacer structure adjacent to the first spacer structure within the second opening to define a third opening smaller than the second opening;

providing a fourth doped region of the second conductivity type within the third doped region aligned with the third opening, wherein the fourth doped region provides a second JFET gate for the second JFET device;

providing a fifth doped region comprising the first conductivity type adjacent to the fourth doped region, wherein the fifth doped region provides a source for the MOSFET device and a second JFET source for the second JFET device; and

providing a sixth doped region comprising the second conductivity type extending through a portion of the fifth doped region and coupled to the second doped region, wherein the sixth doped region provides a body contact for the MOSFET device and a gate contact to the first JFET gate for the second JFET device.

2. The method of claim 1 , wherein providing the fifth doped region comprises:

providing a third spacer structure adjacent to the second spacer structure within the third opening to define a fourth opening smaller than the third opening; and

forming the fifth doped region aligned with the fourth opening.

3. The method of claim 1 , wherein:

the MOSFET device comprises a silicon carbide (SiC) MOSFET device.

4. The method of claim 1 , wherein providing the first doped region comprises:

forming the first JFET channel region with a dopant concentration N D , a width W, and a length L configured to cause pinch-off of short-circuit current of the MOSFET device during a short-circuit event.

5. The method of claim 4 , wherein providing the first doped region comprises:

providing the first JFET channel region with a channel dose N D *W for a value of L configured to cause the pinch-off to occur at a specified short-circuit current.

6. The method of claim 1 , wherein providing the second doped region comprises:

first ion implanting a first portion of the second doped region at a first ion implant energy; and

second ion implanting a second portion of the second doped region at a second ion implant energy greater than the first ion implant energy;

wherein:

the second portion is interposed between the first side of the body of semiconductor material and the first portion; and

the first portion has a higher peak dopant concentration than the second portion.

7. The method of claim 6 , wherein:

the first ion implanting occurs before providing the first spacer structure; and

the second ion implanting occurs after providing the first spacer structure.

8. The method of claim 6 , wherein:

the first ion implant energy is about 150 keV;

the first ion implanting comprises an ion implant dose between about 1.0×10 13 atoms/cm 2 and about 6.0×10 13 atoms/cm 2 ;

the second ion implant energy is greater than about 400 keV; and

the second ion implanting comprises an ion implant dose between about 1.0×10 14 atoms/cm 2 and about 6.0×10 14 atoms/cm 2 .

9. The method of claim 1 , wherein providing the first doped region comprises:

ion implanting a dopant of the first conductivity type using a plurality of ion implant doses including at least a first ion implant dose at a first ion implant energy in a range from about 30 keV to about 320 keV and at least a second ion implant dose at a second ion implant energy in a range from about 460 keV to about 900 keV.

10. The method of claim 9 , wherein providing the first doped region comprises:

ion implanting with the dopant comprising nitrogen with a cumulative ion implant dose between about 4.0×10 12 atoms/cm 2 and about 6.5×10 12 atoms/cm 2 .

11. The method of claim 1 , wherein:

providing the body of semiconductor material comprises:

providing the semiconductor region comprising silicon carbide (SiC); and

providing the semiconductor region with a dopant concentration; and

providing the first doped region comprises providing the first doped region comprising a peak dopant concentration greater than the dopant concentration of the semiconductor region.

12. The method of claim 1 , further comprising:

providing a conductor coupled to the sixth doped region, the fifth doped region, and the fourth doped region.

13. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a semiconductor region of a first conductivity type, a first side, and a second side opposite to the first side, the semiconductor region comprising a first dopant concentration, wherein the semiconductor substrate provides a drain for a MOSFET device and a first JFET drain for a first JFET device, and wherein at least the semiconductor region comprises silicon carbide (SiC);

providing a first doped region at the first side extending into the semiconductor region and comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration, wherein the first doped region provides a first JFET channel region for the first JFET device;

providing a second doped region within the first doped region extending from the first side into the first doped region and comprising a second conductivity type opposite to the first conductivity type, wherein:

the second doped region provides a body region for the MOSFET device and a gate region for the first JFET device;

the second doped region comprises a first portion and a second portion;

the first portion is interposed between the first side and the second portion; and

the second portion has a higher peak dopant concentration than the first portion; and

providing a third doped region within and self-aligned to the second doped region and comprising the first conductivity type, wherein the third doped region provides a first JFET source for the first JFET device.

14. The method of claim 13 , wherein providing the second doped region comprises:

ion implanting the first portion of the second doped region at a first ion implant energy less than about 150 keV and a first ion implant dose in a range from about 1.0×10 13 atoms/cm 2 and about 6.0×10 13 atoms/cm 2 ; and

ion implanting the second portion of the second doped region at a second ion implant energy greater than about 400 keV and a second ion implant dose in a range from about 1.0×10 14 atoms/cm 2 and about 6.0×10 14 atoms/cm 2 .

15. The method of claim 13 , wherein providing the first doped region comprises:

ion implanting a dopant of the first conductivity type using a plurality of ion implant doses with at least one ion implant dose at ion implant energy in range from about 650 keV to about 900 keV,

wherein:

the plurality of ion implant doses provides a total ion implant dose in a range from about 5.0×10 12 atoms/cm 2 to about 6.0×10 12 atoms/cm 2 .

16. The method of claim 13 , wherein providing the first doped region comprises:

forming the first JFET channel region with a doping concentration N D , a width W, and a length L configured to cause pinch-off of short-circuit current of the MOSFET device during a short-circuit event.

17. The method of claim 13 , wherein:

the second doped region provides a first JFET gate for a second JFET device;

the third doped region provides a second JFET channel region for the second JFET device and a second JFET drain for the second JFET device; and

the method further comprises:

providing a fourth doped region comprising the second conductivity type within and self-aligned to the third doped region, wherein the fourth doped region provides a second JFET gate for the second JFET device;

providing a fifth doped region comprising the first conductivity type adjacent to the fourth doped region, wherein the fifth doped region provides a source for the MOSFET device and a second JFET source for the second JFET device;

providing a sixth doped region comprising the second conductivity type extending through a portion of the fifth doped region and connected to the first portion of the second doped region, wherein the sixth doped region provides a body contact for the MOSFET device, a gate contact to the gate region for the first JFET device, and a gate contact to the first JFET gate for the second JFET device; and

providing a conductor electrically coupling the sixth doped region, the fifth doped region, and the fourth doped region together.

Assignments (3)

Continuity (1)

References Cited (13)