Circuitry and methods for mitigating gradient effects in image sensors
An image sensor may include an array of pixels and associated delay calibration circuitry for determining an amount of delay for row control signals. The delay calibration circuitry can include circuitry for generating a calibration row control signal, circuitry for propagating the calibration row control signal down a row of dummy pixels, and one or more sampling circuits coupled to one or more tap points in the row of dummy pixels for monitoring when the calibration row control signal arrives at the one or more tap points. The array of pixels can output signals during normal operation. The image sensor may include column readout circuitry for reading out the signals from the array of pixels. The column readout circuitry can be controlled using sampling signals that are progressively delayed based on count values output from the one or more sampling circuits.
1. An image sensor comprising:
a pixel array; and
delay calibration circuitry including
a row of dummy pixels,
a calibration row driver configured to output a row control signal to the row of dummy pixels via a row line, and
a plurality of sampling circuits coupled to tap points along the row line and that are used to measure a propagation delay of the row control signal along the row line.
2. The image sensor of claim 1 , wherein the plurality of sampling circuits comprises a plurality of time-to-digital converters.
3. The image sensor of claim 2 , wherein at least one of the plurality of time-to-digital converters comprises an analog-to-digital converter and a counter.
4. The image sensor of claim 1 , wherein at least one of the dummy pixels comprises a photodiode having an anode coupled to a ground power supply line and having a cathode coupled to a positive power supply line or the ground power supply line.
5. The image sensor of claim 1 , wherein the plurality of sampling circuits includes only:
a first sampling circuit coupled to a leading dummy pixel in the row of dummy pixels;
a second sampling circuit coupled to a middle dummy pixel in the row of dummy pixels; and
a third sampling circuit coupled to a last dummy pixel in the row of dummy pixels.
6. The image sensor of claim 1 , wherein the plurality of sampling circuits comprises a plurality of sampling circuits coupled to a subset of dummy pixels in the row of dummy pixels.
7. The image sensor of claim 1 , wherein the delay calibration circuitry further comprises:
interpolation circuitry configured to receive count values from the plurality of sampling circuits.
8. The image sensor of claim 7 , wherein the delay calibration circuitry further comprises:
a column sampling signal delay generator configured to receive interpolated values from the interpolation circuitry and to generate sampling signals that are progressively delayed with respect to one another based on the interpolated values.
9. The image sensor of claim 8 , further comprising:
column readout circuitry configured to receive signals from the pixel array and controlled by the sampling signals generated by the column sampling signal delay generator.
10. The image sensor of claim 1 , wherein the delay calibration circuitry further comprises:
an additional calibration row driver configured to output an additional row control signal to the row of dummy pixels via the row line.
11. The image sensor of claim 10 , wherein the calibration row driver is disposed at a first end of the row of dummy pixels and wherein the additional calibration row driver is disposed at a second end opposing the first end of the row of dummy pixels.
12. The image sensor of claim 1 , wherein the delay calibration circuitry further comprises:
an additional row of dummy pixels; and
an additional calibration row driver configured to output an additional row control signal to the additional row of dummy pixels via an additional row line.
13. Imaging circuitry comprising:
a pixel array; and
delay calibration circuitry including
a row of dummy pixels,
a calibration row driver configured to output a row control signal to the row of dummy pixels via a row line, and
at least one sampling circuit coupled to one or more dummy pixels in the row of dummy pixels and that is used to measure a propagation delay of the row control signal along the row line.
14. Imaging circuitry of claim 13 , wherein the delay calibration circuitry further comprises:
an additional row of dummy pixels; and
an additional calibration row driver configured to output an additional row control signal to the additional row of dummy pixels via an additional row line.
15. The imaging circuitry of claim 13 , wherein at least one of the dummy pixels comprises a photodiode having an anode coupled to a first power supply line and having a cathode coupled to a second power supply line different than the first power supply line.
16. The imaging circuitry of claim 13 , wherein the at least one sampling circuit comprises a time-to-digital converter that includes an analog-to-digital converter and a counter.
17. The imaging circuitry of claim 13 , wherein the at least one sampling circuit is coupled to a leading dummy pixel in the row of dummy pixels via a first path and is coupled to a last dummy pixel in the row of dummy pixels via a second path, and wherein the first and second paths have equal lengths.
18. The imaging circuitry of claim 17 , wherein the delay calibration circuitry further comprises:
delay calculation and computation circuitry configured to receive count values from the at least one sampling circuit and configured to compute a difference value based on the received count values; and
a column sampling signal delay generator configured to generate sampling signals that are progressively delayed with respect to one another based on the computed difference value.
19. The imaging circuitry of claim 18 , further comprising:
column readout circuitry configured to receive signals from the pixel array and controlled by the sampling signals generated by the column sampling signal delay generator.
20. A method of operating an image sensor, comprising:
generating a calibration row control signal;
propagating the calibration row control signal down a row of dummy pixels;
with one or more sampling circuits coupled to one or more tap points in the row of dummy pixels, monitoring when the calibration row control signal arrives at the one or more tap points as the calibration row control signal propagates down the row of dummy pixels;
outputting signals from a pixel array separate from the row of dummy pixels; and
controlling column readout circuitry that receives the signals from the pixel array using sampling signals that are progressively delayed based on count values output from the one or more sampling circuits.