Vertical transistor with reduced cell height
A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.
1. A semiconductor structure comprising:
a vertical semiconductor channel region;
a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region;
a metal gate disposed around the vertical semiconductor channel region, wherein a first portion of the metal gate is above the vertical semiconductor channel region; and
a gate contact entirely above the vertical semiconductor channel region, wherein a portion of the gate contact is directly above a portion of the vertical semiconductor channel region.
2. The semiconductor structure according to claim 1 , further comprising:
a composite spacer laterally separating the first portion of the metal gate from a top source drain region.
3. The semiconductor structure according to claim 1 , further comprising:
a spacer vertically separating a second portion of the metal gate from a bottom most surface of a top source drain region.
4. The semiconductor structure according to claim 1 , wherein a second portion of the metal gate is below a topmost surface of the vertical semiconductor channel region.
5. The semiconductor structure according to claim 1 , wherein a vertical sidewall of the metal gate directly below the gate contact is substantially flush with a vertical sidewall of the bottom source drain region.
6. A semiconductor structure comprising:
a vertical semiconductor channel region;
a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region;
a metal gate disposed around the vertical semiconductor channel region; and
a top source drain region above the vertical semiconductor channel region, wherein a topmost surface of the metal gate is substantially flush with a topmost surface of the top source drain region.
7. The semiconductor structure according to claim 6 , further comprising:
a composite spacer laterally separating the metal gate from the top source drain region.
8. The semiconductor structure according to claim 6 , further comprising:
a gate contact entirely above the vertical semiconductor channel region and directly contacting the topmost surface of the metal gate.
9. The semiconductor structure according to claim 6 , further comprising:
a gate contact above the vertical semiconductor channel region, wherein a portion of a gate contact is directly above a portion of the vertical semiconductor channel region.
10. The semiconductor structure according to claim 6 , wherein a first portion of the metal gate is above a topmost surface of the vertical semiconductor channel region and a second portion of the metal gate is below the topmost surface of the vertical semiconductor channel region.
11. The semiconductor structure according to claim 6 , wherein vertical sidewalls at opposite ends of the vertical semiconductor channel region are substantially flush with vertical sidewalls of the bottom source drain region.
12. A semiconductor structure comprising:
two vertical semiconductor channel regions aligned and arrange end-to-end;
a bottom source drain region arranged on a substrate at a bottom of each of the two vertical semiconductor channel regions;
a metal gate disposed around the two vertical semiconductor channel regions, wherein a first portion of the metal gate situated between the two vertical semiconductor channel regions extends above the two vertical semiconductor channel regions; and
a single gate contact entirely above the two vertical semiconductor channel regions, wherein at least a portion of the single gate contact is directly above at least a portion of the two vertical semiconductor channel regions.
13. The semiconductor structure according to claim 12 , further comprising:
a composite spacer laterally separating the first portion of the metal gate from a top source drain region.
14. The semiconductor structure according to claim 12 , further comprising:
a spacer vertically separating a second portion of the metal gate from a bottom most surface of a top source drain region.
15. The semiconductor structure according to claim 12 , wherein a second portion of the metal gate is below a topmost surface of the two vertical semiconductor channel regions.
16. The semiconductor structure according to claim 12 , wherein a vertical sidewall of the metal gate directly below the single gate contact is substantially flush with a vertical sidewall of the bottom source drain region.