Battery pack controller and control method
Enhanced battery pack controllers and control methods are disclosed. One illustrative battery pack controller includes: a monitor circuit that couples to a battery pack load terminal to detect when a voltage of the battery pack load terminal indicates a load condition; a fault detection circuit that couples to a current path through an array of one or more battery cells to detect when a current indicates a fault condition; a switch control circuit that selectively de-asserts a discharge transistor control pin, asserts the discharge transistor control pin, and ramps a voltage or current of the discharge transistor control pin in an open loop fashion for at least 10 ms; and a status detection circuit that in the absence of a fault condition causes the switch control circuit to perform said ramping responsive to detection of the load condition while the discharge transistor control pin is de-asserted.
1 . A battery pack controller that comprises:
a monitor circuit that couples to a battery pack load terminal to detect when a voltage of the battery pack load terminal indicates a load condition;
a fault detection circuit that couples to a current path through an array of one or more battery cells to detect when a current indicates a fault condition;
a switch control circuit that selectively de-asserts a discharge transistor control pin, asserts the discharge transistor control pin, and ramps a voltage or current of the discharge transistor control pin in an open loop fashion for at least 10 ms; and
a status detection circuit that in the absence of a fault condition causes the switch control circuit to perform said ramping responsive to detection of the load condition while the discharge transistor control pin is de-asserted,
wherein the monitor circuit further couples to a battery pack charge terminal that is shared with or separate from the battery pack load terminal to detect when a voltage of the battery pack charge terminal indicates a charge condition,
wherein the switch control circuit selectively de-asserts a charge transistor control pin, asserts the charge transistor control pin, and partially asserts the charge transistor control pin for at least 30 s, and
wherein, responsive to the detection of the charge condition, the status detection circuit causes the switch control circuit to partially assert the charge transistor control pin if the array of one or more battery cells is depleted and otherwise causes the switch control circuit to assert the charge transistor control pin.
2 . The battery pack controller of claim 1 , wherein the status detection circuit causes the switch control circuit to de-assert the discharge transistor control pin when the fault condition is detected.
3 . The battery pack controller of claim 1 , wherein the switch control circuit ramps the voltage or current by charging or discharging a capacitance via a resistance.
4 . The battery pack controller of claim 1 , wherein the switch control circuit ramps the voltage or current by charging or discharging a capacitance using a current source or current sink.
5 . The battery pack controller of claim 1 , wherein the switch control circuit uses a charge pump to generate a drive voltage for asserting or partially asserting the charge transistor control pin.
6 . The battery pack controller of claim 5 , wherein the status detection circuit uses a feedback loop to regulate the drive voltage for partially asserting the charge transistor control pin.
7 . A battery pack control method that comprises:
monitoring a current path through an array of one or more battery cells for a fault condition;
monitoring a battery pack load terminal to detect when a voltage of the battery pack load terminal indicates a load condition;
monitoring a battery pack charge terminal to detect when a voltage of the battery pack charge terminal indicates a charge condition;
responsive to detecting the load condition and in the absence of a fault condition, asserting a discharge transistor control pin after ramping a voltage or current of a discharge transistor control pin for at least 10 ms; and
responsive to detecting the charge condition, partially asserting a charge transistor control pin for at least 30 s if the array of one or more battery cells is depleted and otherwise asserting the charge transistor control pin.
8 . The battery pack control method of claim 7 , further comprising de-asserting the discharge transistor control pin when the fault condition is detected.
9 . The battery pack control method of claim 7 , wherein said ramping includes charging or discharging a capacitance via a resistance.
10 . The battery pack control method of claim 7 , wherein said ramping includes charging or discharging a capacitance using a current source or current sink.
11 . The battery pack control method of claim 7 , wherein a charge pump generates a drive voltage for asserting or partially asserting the charge transistor control pin.
12 . The battery pack control method of claim 11 , further comprising regulating the drive voltage using a feedback loop.
13 . The battery pack control method of claim 7 , wherein the battery pack load terminal is separate from the battery pack charge terminal.
14 . The battery pack control method of claim 13 , wherein the load condition is indicated by the voltage of the battery pack load terminal being below a battery cell array voltage.
15 . The battery pack control method of claim 14 , wherein the charge condition is indicated by the voltage of the battery pack charge terminal being above the battery cell array voltage.
16 . The battery pack control method of claim 13 , wherein the load condition is indicated by the voltage of the battery pack load terminal being positive.
17 . The battery pack control method of claim 14 , wherein the charge condition is indicated by the voltage of the battery pack charge terminal being negative.
18 . The battery pack control method of claim 7 , wherein the battery pack load terminal is shared with the battery pack charge terminal.
19 . The battery pack control method of claim 18 , wherein the load condition is indicated by the voltage of the battery pack load terminal being below a battery cell array voltage.
20 . The battery pack control method of claim 19 , wherein the charge condition is indicated by the voltage of the battery pack charge terminal being above the battery cell array voltage.
21 . The battery pack control method of claim 18 , wherein the load condition is indicated by the voltage of the battery pack load terminal being positive.
22 . The battery pack control method of claim 21 , wherein the charge condition is indicated by the voltage of the battery pack charge terminal being negative.
23 . A battery pack that comprises:
a battery cell array;
a charge transistor configured to control a charging current flow to the battery cell array from a battery pack charge terminal;
a discharge transistor configured to control a load current flow from the battery cell array to a battery pack load terminal;
a battery pack controller that includes:
a fault detection circuit configured to detect a fault condition of the battery cell array;
a monitor circuit configured to detect when a voltage of the battery pack load terminal indicates a load condition and configured to detect when a voltage of the battery pack charge terminal indicates a charge condition;
a switch control circuit configured to selectively de-assert a discharge transistor control pin, assert the discharge transistor control pin, and ramp a voltage or current of the discharge transistor control pin in an open loop fashion for at least 10 ms, and configured to selectively de-assert a charge transistor control pin, assert the charge transistor control pin, and partially assert the charge transistor control pin for at least 30 s; and
a status detection circuit configured to, in the absence of the fault condition, cause the switch control circuit to perform said ramping responsive to detection of the load condition while the discharge transistor control pin is de-asserted, and, responsive to detection of the charge condition, to cause the switch control circuit to partially assert the charge transistor control pin for at least 30 s if the battery cell array is depleted and otherwise to cause the switch control circuit to assert the charge transistor control pin.
24 . The battery pack of claim 23 , wherein the switch control circuit is configured to use a charge pump to generate a drive voltage for asserting or partially asserting the charge transistor control pin, and wherein the status detection circuit is configured to regulate the drive voltage with a feedback loop for partially asserting the charge transistor control pin.
25 . The battery pack of claim 24 , wherein the switch control circuit is configured to de-assert the discharge transistor control pin when the fault condition is detected.
26 . The battery pack of claim 23 , wherein the load condition is indicated by the voltage of the battery pack load terminal being positive, and wherein the charge condition is indicated by the voltage of the battery pack charge terminal being negative.