Up-diffusion suppression in a power MOSFET

1. A method for preparing a substrate for fabricating a vertical MOSFET device, the method comprising:

forming a first epitaxial layer on a silicon wafer;

forming an ion-implanted capping layer in the first epitaxial layer; and

forming a device layer over the first epitaxial layer,

the silicon wafer being a phosphorus doped n + silicon wafer, the first epitaxial layer being doped with phosphorus, the ion-implanted capping layer being an arsenic-implanted buried layer, and

wherein forming the device layer over the first epitaxial layer includes forming a source of the device in the device layer and forming a drain of the device in the silicon wafer.

2. The method of claim 1 , wherein forming the ion-implanted capping layer in the first epitaxial layer includes:

forming a screen oxide on the first epitaxial layer;

implanting arsenic ions through the screen oxide;

thermally annealing the ion implanted wafer; and

stripping the screen oxide.

3. The method of claim 2 , wherein the ion-implanted capping layer has a peak arsenic dopant concentration of about 5×10 +17 atoms/cc to 5×10 +19 atoms/cc.

4. The method of claim 2 , wherein implanting arsenic ions through the screen oxide includes implanting multiple doses of the arsenic ions at multiple implant energies.

5. The method of claim 4 , wherein implanting multiple doses of the arsenic ions at multiple implant energies includes implanting each of the multiple doses of the arsenic ions in a new epitaxial layer grown after annealing and stripping the screen oxide of the previous arsenic implantation.

6. The method of claim 1 , wherein the forming the device layer over the first epitaxial layer includes forming a second epitaxial layer having phosphorus dopant concentrations in a range of about 10 +15 to 5×10 +17 atoms/cm 3 .

7. A method for preparing a substrate for fabricating a vertical MOSFET device, the method comprising:

disposing a first epitaxial layer on a silicon wafer;

forming an ion-implanted capping layer in the first epitaxial layer disposed on the silicon wafer, the silicon wafer and the ion-implanted capping layer being doped with dopants of a same conductivity type, the silicon wafer being doped with a first dopant to form a drain region of the vertical MOSFET device, the ion-implanted capping layer being doped with a second dopant, the first dopant having a higher diffusivity in silicon than a lower diffusivity of the second dopant in silicon; and

disposing a second epitaxial layer on the first epitaxial layer,

the first epitaxial layer including the ion-implanted capping layer having a thickness configured to contain up-diffusion of the first dopant having the higher diffusivity from the silicon wafer in the first epitaxial layer in thermal processes for fabricating the vertical MOSFET device,

the ion-implanted capping layer configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into the second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.

8. The method of claim 7 , wherein the silicon wafer is a phosphorus doped n + silicon wafer, the ion-implanted capping layer is an arsenic-implanted buried layer.

9. The method of claim 7 , wherein the ion-implanted capping layer is formed by a dose of arsenic ions implanted in the first epitaxial layer at an implant energy.

10. The method of claim 9 , wherein the dose is in a range of about 2E13 atoms/cm 2 to 1E16 atoms/cm 2 and the implant energy is in a range of about 40 keV to 200 keV.

11. The method of claim 10 , wherein the ion-implanted capping layer is annealed at a temperature in a range of about 900° C. to 1200° C. for an anneal time in a range of about 30 minutes to 240 minutes.

12. The method of claim 11 , wherein the ion-implanted capping layer after annealing has a peak arsenic dopant concentration in a range of about 1×10 +18 to 5×10 +19 atoms/cc, and wherein the first epitaxial layer and second epitaxial layer as first disposed on silicon wafer have phosphorus dopant concentrations in a range of about 10 +14 to 5×10 +17 atoms/cc.

13. A method for fabricating a vertical MOSFET device, the method comprising:

forming a drain of the vertical MOSFET device in a heavily doped silicon substrate; and

forming a semiconductor mesa including a drift region of the vertical MOSFET device, the semiconductor mesa disposed on a first epitaxial layer, the first epitaxial layer disposed on the heavily doped silicon substrate, the semiconductor mesa being formed in a second epitaxial layer disposed on the first epitaxial layer,

forming an ion-implanted capping layer in the first epitaxial layer, the ion-implanted capping layer having a thickness t configured to contain up-diffusion of a first dopant from the heavily doped silicon substrate into the first epitaxial layer in thermal processes for fabricating the vertical MOSFET device,

the ion-implanted capping layer containing up-diffusion of the first dopant from the heavily doped silicon substrate through the ion-implanted capping layer into the semiconductor mesa such that a concentration of the first dopant in the semiconductor mesa is lower than a concentration of the first dopant in the first epitaxial layer.

14. The method of claim 13 , wherein the heavily doped silicon substrate is a phosphorus doped n + silicon wafer, and wherein the ion-implanted capping layer is an arsenic-implanted buried layer, wherein the ion-implanted capping layer in the vertical MOSFET device has a peak arsenic dopant concentration in a range of about 5×10 +17 to 10 +19 atoms/cm 3 , and wherein the ion-implanted capping layer is disposed in a first epitaxial layer grown on the phosphorus doped n + silicon wafer.

15. The method of claim 13 , wherein the drift region of the vertical MOSFET device included in the semiconductor mesa has phosphorus dopant concentration in a range of about 1×10 +15 to 3×10 +17 atoms/cm 3 .

16. The method of claim 14 , wherein a net dopant concentration profile has a decreasing value from the drain of the vertical MOSFET device to a valley region in the first epitaxial layer, an increasing value from the valley region to a peak value at a peak in the ion-implanted capping layer, and a decreasing value from the peak into the drift region of the vertical MOSFET device.

17. A method of fabricating a MOSFET device, the method comprising:

forming a drain region in a phosphorus doped silicon wafer;

disposing an epitaxial layer doped with phosphorus on the phosphorus doped silicon wafer;

forming a source region in a device layer disposed on the epitaxial layer doped with phosphorus; and

implanting an arsenic ion-implanted capping layer in the epitaxial layer below the source region in the device layer and above the drain region formed in the phosphorus doped silicon wafer,

the arsenic ion-implanted capping layer containing up-diffusion of phosphorus dopant from the phosphorus doped silicon wafer through the arsenic ion-implanted capping layer such that a concentration of the phosphorus dopant in the device layer at or above the arsenic ion-implanted capping layer is lower than a concentration of the phosphorus dopant in the epitaxial layer below the arsenic ion-implanted capping layer.

18. The method of claim 17 , wherein the arsenic ion-implanted capping layer comprises a thermally annealed arsenic ion implanted layer.

19. The method of claim 17 , wherein the arsenic ion-implanted capping layer comprises multiple doses of arsenic ions at multiple implant energies.

20. The method of claim 19 , wherein each of the multiple doses of the arsenic ions is implanted in a new epitaxial layer grown after annealing and stripping a screen oxide of a previous arsenic implantation.