Apparatuses and methods for coupling a plurality of semiconductor devices
Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.
1. An apparatus, comprising:
a memory array configured to store data;
a terminal;
an input/output circuit configured to receive data from the memory array and provide read data and receive write data to be stored in the memory array, wherein the input/output circuit is coupled to the terminal and configured to provide the read data to the terminal and configured to receive the write data from the terminal;
a command and address input circuit configured to receive command and address signals;
first and second bond pads; and
a U-shaped conductive structure coupled to the terminal and including a first portion extending between and coupled to the terminal and the first bond pad and further including a second portion extending between and coupled to the terminal and the second bond pad.
2. The apparatus of claim 1 , wherein the U-shaped conductive structure further includes a third portion coupled to the first and second portions and further coupled to the terminal.
3. The apparatus of claim 1 , wherein the terminal comprises a die pad included in a peripheral circuit area.
4. The apparatus of claim 1 , wherein the first and second bond pads are located at an edge and the terminal is located in an area along a center region disposed between memory cell array areas of the memory array.
5. An apparatus, comprising:
a memory array configured to store data;
a terminal;
an input/output circuit configured to receive data from the memory array and provide read data and receive write data to be stored in the memory array;
a command and address input circuit configured to receive command and address signals, wherein the command and address input circuit is coupled to the terminal and configured to receive command and address signals from the terminal;
first and second bond pads; and
a U-shaped conductive structure coupled to the terminal and including a first portion extending between and coupled to the terminal and the first bond pad and further including a second portion extending between and coupled to the terminal and the second bond pad.
6. An apparatus, comprising:
a memory array configured to store data;
a terminal;
an input/output circuit configured to receive data from the memory array and provide read data and receive write data to be stored in the memory array;
a command and address input circuit configured to receive command and address signals;
first and second bond pads, wherein the first bond pad and the second bond pad are coupled together via a conductor; and
a U-shaped conductive structure coupled to the terminal and including a first portion extending between and coupled to the terminal and the first bond pad and further including a second portion extending between and coupled to the terminal and the second bond pad.
7. An apparatus, comprising:
a memory array configured to store data;
a terminal;
an input/output circuit configured to receive data from the memory array and provide read data and receive write data to be stored in the memory array;
a command and address input circuit configured to receive command and address signals;
first and second bond pads;
a U-shaped conductive structure coupled to the terminal and including a first portion extending between and coupled to the terminal and the first bond pad and further including a second portion extending between and coupled to the terminal and the second bond pad; and
a register clock driver circuit coupled to a conductive signal line coupled to the second bond pad.
8. An apparatus, comprising
a semiconductor device;
a register clock driver circuit coupled to a conductive signal line; and
a portion of a serial path of redistribution layer structures and bond pads, the portion coupled between the semiconductor device and the conductive signal line, wherein the serial path extends past the semiconductor device beyond the portion of the serial path between the semiconductor device and the conductive signal line, and wherein a die pad of the semiconductor device is coupled to two redistribution layer structures of the serial path of redistribution layer structures at a same node.
9. The apparatus of claim 8 , wherein the semiconductor device comprises a memory array, and wherein the die pad is located in an area along a center region disposed between memory cell array areas of the memory array.
10. An apparatus, comprising;
a semiconductor device,
a register clock driver circuit coupled to a conductive signal line; and
a portion of a serial path of redistribution layer structures and bond pads, the portion coupled between the semiconductor device and the conductive signal line, wherein the serial path of redistribution layer structures and bond pads comprises a repeated pattern of two redistribution layer structures followed by two bond pads along the serial path.