Pixel circuit and display device having the same
A pixel circuit includes a first driving transistor including a gate electrode connected to a first node, a first electrode to receive a first power voltage, and a second electrode connected to a second node, a second driving transistor including a gate electrode and a second electrode connected to the second node, a first electrode to receive the first power voltage, and a back gate electrode connected to the first node, a write transistor including a first electrode to receive a data voltage and a second electrode connected to the first node, an initialization transistor including a gate electrode to receive an initialization gate signal, a first electrode to receive an initialization voltage, and a second electrode connected to the second node, a storage capacitor connected to the first and second nodes, and a light emitting element connected to the second node and configured to receive a second power voltage.
1. A pixel circuit comprising:
a first driving transistor comprising a gate electrode connected to a first node, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node;
a second driving transistor comprising a gate electrode connected to the second node, a first electrode configured to receive the first power voltage, a second electrode connected to the second node, and a back gate electrode connected to the first node;
a write transistor comprising a gate electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node;
an initialization transistor comprising a gate electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the second node;
a storage capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node; and
a light emitting element comprising a first electrode connected to the second node, and a second electrode configured to receive a second power voltage.
2. The pixel circuit of claim 1 , wherein the first driving transistor further comprises a back gate electrode connected to the second node.
3. The pixel circuit of claim 1 , wherein the first driving transistor further comprises a back gate electrode connected to the first node.
4. The pixel circuit of claim 1 , further comprising an emission transistor configured to apply the first power voltage to the first driving transistor and to the second driving transistor in response to an emission signal.
5. The pixel circuit of claim 1 , further comprising a reference transistor configured to apply a reference voltage to the first node in response to a reference gate signal.
6. The pixel circuit of claim 1 , further comprising a hold capacitor comprising a first electrode configured to receive the first power voltage and a second electrode connected to the second node.
7. The pixel circuit of claim 1 , wherein the write transistor further comprises a back gate electrode connected to the gate electrode of the write transistor, and
wherein the initialization transistor further comprises a back gate electrode connected to the gate electrode of the initialization transistor.
8. The pixel circuit of claim 1 , further comprising a reference transistor configured to apply a reference voltage to the first node in response to a reference gate signal.
9. A pixel circuit comprising:
a first driving transistor comprising a gate electrode connected to a first node, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node;
a second driving transistor comprising a gate electrode connected to the second node, a first electrode connected to a third node, a second electrode connected to the second node, and a back gate electrode connected to the first node;
a write transistor comprising a gate electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second node;
an initialization transistor comprising a gate electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node;
a storage capacitor comprising a first electrode connected to the first node, and a second electrode connected to the fourth node;
a compensation transistor comprising a gate electrode configured to receive a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the first node;
a first emission transistor comprising a gate electrode configured to receive an emission signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the third node;
a second emission transistor comprising a gate electrode configured to receive the emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; and
a light emitting element comprising a first electrode connected to the fourth node, and a second electrode configured to receive a second power voltage.
10. The pixel circuit of claim 9 , wherein the first driving transistor further comprises a back gate electrode connected to the second node.
11. The pixel circuit of claim 9 , wherein the compensation gate signal is the same as the write gate signal.
12. The pixel circuit of claim 9 , further comprising a first bias transistor comprising a gate electrode configured to receive a bias gate signal, a first electrode configured to receive a bias voltage, and a second electrode connected to the second node.
13. The pixel circuit of claim 12 , wherein the bias gate signal is the same as the initialization gate signal.
14. The pixel circuit of claim 12 , further comprising a second bias transistor comprising a gate electrode configured to receive the emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node.
15. A display device comprising:
a display panel comprising pixel circuits; and
a display panel driver configured to drive the display panel,
wherein each of the pixel circuits comprises:
a first driving transistor comprising a gate electrode connected to a first node, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node;
a second driving transistor comprising a gate electrode connected to the second node, a first electrode configured to receive the first power voltage, a second electrode connected to the second node, and a back gate electrode connected to the first node;
a write transistor comprising a gate electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node;
an initialization transistor comprising a gate electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the second node;
a storage capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node; and
a light emitting element comprising a first electrode connected to the second node, and a second electrode configured to receive a second power voltage.
16. The display device of claim 15 , wherein the first driving transistor further comprises a back gate electrode connected to the second node.
17. The display device of claim 15 , wherein the first driving transistor further comprises a back gate electrode connected to the first node.
18. The display device of claim 15 , wherein each of the pixel circuits further comprises an emission transistor configured to apply the first power voltage to the first driving transistor and to the second driving transistor in response to an emission signal.
19. The display device of claim 15 , wherein each of the pixel circuits further comprises a reference transistor configured to apply a reference voltage to the first node in response to a reference gate signal.
20. The display device of claim 15 , wherein each of the pixel circuits further comprises a hold capacitor comprising a first electrode configured to receive the first power voltage, and a second electrode connected to the second node.