IP Library Granted Patent US 11,861,282
Granted Patent B2
US 11,861,282 · App. 18/065,275 · Granted Jan 2, 2024

Integrated circuit fin structure manufacturing method

Inventors: Po-Hsiang Huang (Hsinchu, TW); Fong-Yuan Chang (Hsinchu, TW); Clement Hsingjen Wann (Hsinchu, TW); Chih-Hsin Ko (Hsinchu, TW); Sheng-Hsiung Chen (Hsinchu, TW); Li-Chun Tien (Hsinchu, TW); Chia-Ming Hsu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G06F30/392G06F30/3312G06F30/367G06F30/398H01L21/823821H01L27/0924H01L29/66795H01L29/785G06F2111/20
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Quick Facts
Patent No.
US 11,861,282
App. No.
18/065,275
Granted
Jan 2, 2024
Kind
B2
Abstract

A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.

Claims (73)

1. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming a first plurality of fins extending in a first direction on a substrate;

forming a second plurality of fins extending in the first direction on the substrate adjacent to the first plurality of fins;

forming a third plurality of fins extending in the first direction on the substrate adjacent to the second plurality of fins; and

forming a fourth plurality of fins extending in the first direction on the substrate adjacent to the third plurality of fins,

wherein

the forming each fin of each of the first and fourth pluralities of fins comprises forming one of an n-type fin or a p-type fin,

the forming each fin of each of the second and third pluralities of fins comprises forming the other of the n-type fin or the p-type fin,

the forming each of the first and third pluralities of fins comprises forming a first total number of fins, and

the forming each of the second and fourth pluralities of fins comprises forming a second total number of fins fewer than the first total number of fins.

2. The method of claim 1 , wherein the forming the second total number of fins fewer than the first total number of fins comprises forming the second total number of fins one fewer than the first total number of fins.

3. The method of claim 1 , wherein

the forming the first through fourth pluralities of fins comprises forming the first through fourth pluralities of fins in corresponding first through fourth active areas,

the first and third active areas have a same first height, and

the second and fourth active areas have a same second height less than the first height.

4. The method of claim 3 , wherein

the first and second heights are first and second active area heights of a manufacturing process,

a distance between a first fin of the first plurality of fins and a first fin of the third plurality of fins corresponds to a cell height of the manufacturing process, and

a sum of the first and second total numbers of fins is a maximum total number of fins capable of being included in the cell height in accordance with first and second minimum spacing rules of the first and second active area heights.

5. The method of claim 4 , wherein the cell height has a value ranging from 200 nanometers (nm) to 300 nm.

6. The method of claim 1 , wherein

the forming the first through fourth pluralities of fins corresponds to forming a pattern of the first through fourth pluralities of fins, and

the forming the pattern is part of forming a plurality of patterns of the first through fourth pluralities of fins.

7. The method of claim 1 , further comprising:

forming first through fourth transistors corresponding to the first through fourth pluralities of fins,

wherein the forming each of the first through fourth transistors comprises forming source/drain (S/D) structures in each fin of the corresponding one of the first through fourth pluralities of fins.

8. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming a first plurality of fins extending in a first direction on a substrate;

forming a second plurality of fins extending in the first direction on the substrate adjacent to the first plurality of fins;

forming a third plurality of fins extending in the first direction on the substrate adjacent to the second plurality of fins; and

forming a fourth plurality of fins extending in the first direction on the substrate adjacent to the third plurality of fins,

wherein

the forming each fin of each of the first and fourth pluralities of fins comprises forming one of an n-type fin or a p-type fin,

the forming each fin of each of the second and third pluralities of fins comprises forming the other of the n-type fin or the p-type fin,

the forming each of the first and third pluralities of fins comprises forming a total of three fins, and

the forming each of the second and fourth pluralities of fins comprises forming a total of two fins.

9. The method of claim 8 , wherein

the forming the total of three fins comprises forming the total of three fins within a first active area height of a manufacturing process, and

the forming the total of two fins comprises forming the total of two fins within a second active area height less than the first active area height of the manufacturing process.

10. The method of claim 9 , wherein

a distance between a first fin of the first plurality of fins and a first fin of the third plurality of fins corresponds to a cell height of the manufacturing process, and

a maximum total number of fins capable of being included in the cell height in accordance with first and second minimum spacing rules of the first and second active area heights is equal to five.

11. The method of claim 8 , wherein

the forming the first through fourth pluralities of fins corresponds to forming a pattern of the first through fourth pluralities of fins, and

the forming the pattern is part of forming a plurality of patterns of the first through fourth pluralities of fins.

12. The method of claim 11 , wherein the pattern has a height ranging from 200 nanometers (nm) to 300 nm.

13. The method of claim 8 , further comprising:

forming first through fourth transistors corresponding to the first through fourth pluralities of fins,

wherein the forming each of the first through fourth transistors comprises forming source/drain (S/D) structures in each fin of the corresponding one of the first through fourth pluralities of fins.

14. A method of manufacturing an integrated circuit (IC) structure, the method comprising:

forming a first plurality of fins extending in a first direction on a substrate;

forming a second plurality of fins extending in the first direction on the substrate adjacent to the first plurality of fins;

forming a third plurality of fins extending in the first direction on the substrate adjacent to the second plurality of fins;

forming a fourth plurality of fins extending in the first direction on the substrate adjacent to the third plurality of fins;

forming a fifth plurality of fins on the substrate aligned with a subset of the first plurality of fins and separated from the first plurality of fins by a fin discontinuity region; and

forming a sixth plurality of fins on the substrate aligned with the second plurality of fins and separated from the second plurality of fins by the fin discontinuity region,

wherein

the forming each fin of each of the first, fourth, and fifth pluralities of fins comprises forming one of an n-type fin or a p-type fin,

the forming each fin of each of the second, third, and sixth pluralities of fins comprises forming the other of the n-type fin or the p-type fin,

the forming each of the first and third pluralities of fins comprises forming a first total number of fins, and

the forming each of the second and fourth through sixth pluralities of fins comprises forming a second total number of fins fewer than the first total number of fins.

15. The method of claim 14 , wherein the forming the second total number of fins fewer than the first total number of fins comprises forming the second total number of fins one fewer than the first total number of fins.

16. The method of claim 14 , wherein the forming the fifth plurality of fins aligned with the subset of the first plurality of fins comprises aligning a fin of the first plurality of fins with a space between the fifth and sixth pluralities of fins.

17. The method of claim 14 , wherein

the forming the fifth plurality of fins aligned with the subset of the first plurality of fins comprises aligning a fin of the first plurality of fins with a space, and

the fifth plurality of fins is positioned between the space and the sixth plurality of fins.

18. The method of claim 14 , wherein each of the forming the fifth plurality of fins separated from the first plurality of fins by the fin discontinuity region and the forming the sixth plurality of fins separated from the second plurality of fins by the fin discontinuity region comprises forming the corresponding pluralities of fins separated by a distance ranging from 50 nanometers (nm) to 100 nm.

19. The method of claim 14 , wherein

a distance between a first fin of the first plurality of fins and a first fin of the third plurality of fins corresponds to a cell height of a manufacturing process, and

a sum of the first and second total numbers of fins is a maximum total number of fins capable of being included in the cell height in accordance with minimum spacing rules of the manufacturing process.

20. The method of claim 14 , further comprising:

forming first through sixth transistors corresponding to the first through sixth pluralities of fins,

wherein the forming each of the first through sixth transistors comprises forming source/drain (S/D) structures in each fin of the corresponding one of the first through sixth pluralities of fins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2022
From: HUANG, PO-HSIANG; CHEN, SHENG-HSIUNG; KO, CHIH-HSIN; CHANG, FONG-YUAN; WANN, CLEMENT HSINGJEN; TIEN, LI-CHUN; HSU, CHIA-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 062071/0677 →
Continuity (4)
Continuation 17376413 · Jul 15, 2021
Division 16599552 · Oct 11, 2019
Provisional Application 62753259 · Oct 31, 2018
Related Publication 20230113014A1 · Apr 13, 2023
Cited By (1)
US 12,307,183