Processor performance profiling using trace actions
In a general aspect, a processor can include an instruction processing unit configured to execute a software program that includes a plurality of machine-readable instructions, and a hardware performance monitoring unit. The hardware performance monitoring unit can include a plurality of counters configured to count respective processing events associated with execution of the software program, and a counter overflow monitor configured to generate an indication of a respective counter-overflow trace action in response to overflow of a counter of the plurality of counters. The processor can also include a trace encoder configured to receive the indication of the respective counter-overflow trace action from the hardware performance monitoring unit, and, in response to the indication of the respective counter-overflow trace action, perform the respective counter-overflow trace action.
1. A processor comprising:
an instruction processing unit configured to execute a software program including a plurality of machine-readable instructions;
a hardware performance monitoring unit, the hardware performance monitoring unit including:
a plurality of counters configured to count respective processing events associated with execution of the software program, and
a counter overflow monitor configured to generate an indication of a respective counter-overflow trace action in response to overflow of a counter of the plurality of counters; and
a trace encoder configured to:
receive the indication of the respective counter-overflow trace action from the hardware performance monitoring unit, and
in response to the indication of the respective counter-overflow trace action, perform the respective counter-overflow trace action.
2. The processor of claim 1 , wherein the respective counter-overflow trace action includes encoding a trace packet that includes an address of a machine-readable instruction of the plurality of machine-readable instructions, wherein the address corresponds with the overflow of the counter of the plurality of counters.
3. The processor of claim 2 , wherein:
the indication of the respective counter-overflow trace action includes an identifier of the counter of the plurality of counters, and
the trace packet further includes the identifier of the counter of the plurality of counters.
4. The processor of claim 1 , wherein the respective counter-overflow trace action includes one of:
enabling the trace encoder, or
disabling the trace encoder.
5. The processor of claim 1 , further comprising a trigger block configured to:
administer a plurality of trigger conditions,
receive, from the instruction processing unit, address and data values associated with execution of the software program,
compare the received address and data values with the plurality of trigger conditions, and
in response to a match between a given value of the received address and data values and a trigger condition of the plurality of trigger conditions, indicate a respective trigger trace action,
the trace encoder being further configured to:
receive the indication of the respective trigger trace action, and
in response to the indication of the respective trigger trace action, perform the respective trigger trace action.
6. The processor of claim 5 , wherein the respective trigger trace action includes encoding a trace packet including an address of a machine-readable instruction of the plurality of machine-readable instructions corresponding with the matched trigger condition.
7. The processor of claim 6 , wherein:
the indication of the respective trigger trace action includes an identifier of the trigger condition of the plurality of trigger conditions, and
the trace packet further includes the identifier of the trigger condition of the plurality of trigger conditions.
8. The processor of claim 5 , wherein:
the respective counter-overflow trace action is one of:
a trace enable action,
a trace disable action, or
a trace notify action,
the respective trigger trace action is one of:
the trace enable action,
the trace disable action, or
the trace notify action,
the processor further comprising logic configured to:
combine indications of the trace enable action from the hardware performance monitoring unit with indications of the trace enable action from the trigger block,
combine indications of the trace disable action from the hardware performance monitoring unit with indications of the trace disable action from the trigger block, and
combine indications of the trace notify action from the hardware performance monitoring unit with indications of the trace notify action from the trigger block.
9. The processor of claim 5 , wherein the received address and data values include at least one of:
an instruction address,
a memory address,
an instruction opcode,
a data value stored by the processor, or
a data value read by the processor.
10. The processor of claim 1 , wherein the hardware performance monitoring unit further includes a plurality of initialization registers respectively coupled with the plurality of counters, the plurality of initialization registers being configured to load respective initialization values in the plurality of counters.
11. The processor of claim 1 , wherein a counter of the plurality of counters includes:
a count value field, and
an initialization value field,
the counter being configured to load an initialization value from the initialization value field into the count value field.
12. A processor comprising:
an instruction processing unit configured to execute a software program including a plurality of machine-readable instructions;
a hardware performance monitoring unit configured to provide first trace action indication signals in response to overflow of counters configured to count processing events occurring during execution of the software program;
a trigger block configured to provide second trace action indication signals in response to matching of trigger conditions during execution of the software program;
combinational logic configured to respectively combine the first trace action indication signals with the second trace action indication signals to produce combined trace action indication signals; and
a trace encoder configured to:
receive the combined trace action indication signals, and
in response to the combined trace action indication signals, perform respective trace actions.
13. The processor of claim 12 , wherein the respective trace actions include:
enabling the trace encoder,
encoding a trace packet including an address of a machine-readable instruction of the plurality of machine-readable instructions, and
disabling the trace encoder.
14. The processor of claim 13 , wherein the address of the machine-readable instruction of the plurality of machine-readable instructions corresponds with one of:
a counter overflow, or
a matched trigger condition.
15. The processor of claim 14 , wherein the trace packet includes one of:
an indication of a counter that overflowed, or
the matched trigger condition.
16. The processor of claim 12 , wherein the trigger conditions are based on address and data values associated with execution of the software program.
17. A method of operating a processor, the method comprising:
executing, by an instruction processing unit, a software program that includes a plurality of machine-readable instructions;
counting, by a hardware performance monitoring unit having a plurality of counters, respective processing events associated with execution of the software program;
indicating, by the hardware performance monitoring unit in response to overflow of a counter of the plurality of counters, a respective counter-overflow trace action; and
receiving, by a trace encoder, the indication of the respective counter-overflow trace action from the hardware performance monitoring unit; and
performing, by the trace encoder in response to the indication of the respective counter-overflow trace action, the respective counter-overflow trace action.
18. The method of claim 17 , wherein the respective counter-overflow trace action includes encoding a trace packet including an address of a machine-readable instruction of the plurality of machine-readable instructions corresponding with the overflow of the counter of the plurality of counters.
19. The method of claim 17 , further comprising:
administering, by a trigger block, a plurality of trigger conditions;
receiving, by the trigger block from the instruction processing unit, address and data values associated with execution of the software program;
comparing, by the trigger block, the received address and data values with the plurality of trigger conditions;
indicating, by the trigger block in response to a match between a given value of the received address and data values and a trigger condition of the plurality of trigger conditions, a respective trigger trace action;
receiving, by the trace encoder, the indication of the respective trigger trace action; and
performing, by the trace encoder in response to the indication of the respective trigger trace action, the respective trigger trace action.
20. The method of claim 19 , wherein the respective trigger trace action includes encoding a trace packet including an address of a machine-readable instruction of the plurality of machine-readable instructions corresponding with the matched trigger condition.