HEIGHT ADAPTABLE MULTILAYER SPACER
The invention relates to a metal layer stack for use in electronic components, in particular as a spacer in power electronic components, comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two. Additionally, the invention relates to a process for preparing the metal layer stack and a semiconductor module comprising such a metal layer stack.
1 . A metal layer stack for use in electronic components comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two.
2 . The metal layer stack according to claim 1 , wherein where the contact material layer comprises a sinter material.
3 . The metal layer stack according to claim 1 , wherein the mean thickness of the contact material layer is in the range from 10 μm to 100 μm.
4 . The metal layer stack according to claim 1 , wherein the bulk metal layer comprises a metal selected from the group consisting of copper, molybdenum, tungsten, silver, aluminium and combinations thereof.
5 . The metal layer stack according to claim 1 , where the mean thickness of the bulk metal layers is in the range from 50 μm to 600 μm.
6 . The metal layer stack according to claim 1 , wherein the sinter material is a sinter precursor or a sintered joint.
7 . The metal layer stack according to claim 1 , wherein the sinter material comprises a metal selected from the group consisting of silver, copper, aluminium, tin, indium, bismuth, nickel and zinc.
8 . A semiconductor module wherein a first surface of a semiconductor chip is in contact with a first contact material layer of the metal layer stack according to claim 1 .
9 . The semiconductor module according to claim 8 , wherein a substrate is attached to the last contact material layer of the metal layer stack.
10 . The semiconductor module according to claim 8 , wherein at least one gate runner is arranged between the semiconductor chip and the metal layer stack.
11 . The semiconductor module according to claim 8 , wherein the metal layer stack functions as a spacer.
12 . The semiconductor module according to claim 8 , wherein a second surface of the semiconductor chip opposite to the first surface contacts a second substrate.
13 . The semiconductor module according to claim 8 , wherein one or more substrates of the semiconductor module are selected from the group consisting of metal ceramic substrates, organic substrates, insulated metal substrates, lead frames and ceramic substrates.
14 . A precursor for a spacer comprising a metal layer stack according to claim 1 , wherein at least the first or the last contact material layer of the metal layer stack comprises a sinter precursor.
15 . A process for producing a metal layer stack, preferably according to claim 1 , the process comprising the steps of:
a) providing a carrier,
b) providing a first layer assembly comprising a contact material precursor layer arranged on a bulk metal layer,
c) arranging the layer assembly on the carrier such that the contact material precursor layer is in contact with the carrier,
d) providing a second layer assembly comprising a contact material precursor arranged on a bulk metal layer,
e) arranging the second layer assembly on the bulk metal layer of the first layer assembly such that the contact material precursor of the second layer assembly is in contact with the bulk metal layer of the first layer assembly, and
f) optionally repeating steps d) and e).
16 . The process according to claim 15 , comprising a step g) of converting the contact material precursor layers into layers of joint material.