Charge injection-related and switching error-related offset reduction by local chopping of switched-capacitor circuits
Switched-capacitor circuits having reduced charge injection offset are implemented by differentially interchanging pairs of charge transfer switches of the switched-capacitor circuit at a frequency other than the sampling frequency of the switched-capacitor circuit, thereby chopping the switch signal paths. The circuits include a pair of capacitors, a switching circuit that alternatively charges the pair of capacitors from a differential input and transfers the charge from the pair of capacitors, according to corresponding phases of a reference sampling clock. The circuits also include a chopping circuit that alternates differential connections to at least some of the switches. The chopping circuit is operated at a chopping frequency, so that DC offset caused by charge-injection in the switching circuit due to the reference sampling clock coupling through the switches of the switching circuit is removed by modulating the charge injection of the switching circuit away from DC.
1 . A differential switched-capacitor circuit, comprising:
two or more pairs of charge transfer switches operating at a sampling frequency; and
an associated two or more pairs of capacitors coupled to the two or more pairs of charge transfer switches by a corresponding two or more quads of chopping switches, wherein each terminal of the two or more pairs of charge transfer switches have connections differentially interchanged by the corresponding quad of chopping switches operating at a chopping frequency different from the sampling frequency to modulate charge injection through the two or more pairs of charge transfer switches away from DC.
2 . The differential switched-capacitor circuit of claim 1 , wherein the sampling frequency is a multiple of the chopping frequency, whereby the two or more quads of chopping switches average the charge injection in half-periods of the chopping frequency and effectively subtract injected charge in consecutive half-periods.
3 . The differential switched-capacitor circuit of claim 2 , wherein the sampling frequency is a multiple greater than or equal to 100 of the chopping frequency.
4 . A method of reducing DC offset due to charge injection asymmetry in a differential switched circuit, the method comprising:
operating two or more pairs of charge transfer switches at a sampling frequency; and
coupling an associated two or more pairs of capacitors to the two or more pairs of charge transfer switches by a corresponding two or more quads of chopping switches, wherein each terminal of the two or more pairs of charge transfer switches have connections differentially interchanged by the corresponding quad of chopping switches operating at a chopping frequency different from the sampling frequency to modulate charge injection through the two or more pairs of charge transfer switches away from DC.
5 . The method of claim 4 , wherein the sampling frequency is a multiple of the second frequency, whereby the two or more quads of chopping switches average the charge injection in half-periods of the chopping frequency and effectively subtract injected charge in consecutive half-periods.
6 . The method of claim 5 , wherein the sampling frequency is a multiple greater than or equal to 100 of the chopping frequency.
7 . A differential switched-capacitor circuit comprising:
a pair of input sampling capacitors;
a switching circuit including a plurality of charge transfer switches that alternatively charge the pair of input sampling capacitors from a differential input in a first phase of a reference sampling clock and transfer charge from the pair of input sampling capacitors in a second phase of the reference sampling clock; and
a chopping circuit that alternates connections to each terminal of at least some of the charge transfer switches of the switching circuit between differential pairs of signals through the switching circuit, wherein the chopping circuit is operated at a chopping frequency different from a frequency of the reference sampling clock, whereby a DC offset caused by charge-injection asymmetry in the differential switched-capacitor circuit due to the reference sampling clock coupling through the charge transfer switches of the switching circuit is removed by modulating a charge injection of the switching circuit away from DC.
8 . The differential switched-capacitor circuit of claim 7 , wherein a frequency of the reference sampling clock is a multiple of the second frequency, whereby the chopping circuit averages the charge injection in half-periods of the second frequency and effectively subtracts injected charge in consecutive half-periods.
9 . The differential switched-capacitor circuit of claim 8 , wherein the frequency of the reference sampling clock is a multiple greater than or equal to 100 of the chopping frequency.
10 . The differential switched-capacitor circuit of claim 7 , wherein the switching circuit is an input circuit of a differential integrator or gain-stage that accumulates the charge injection on a pair of feedback capacitors coupled between outputs and inputs of a differential amplifier, wherein the asymmetry in charge injection in the differential switched-capacitor circuit results in the DC offset, and wherein the switching circuit transfers charge from the pair of input sampling capacitors to the pair of feedback capacitors of the differential integrator or gain-stage.
11 . The differential switched-capacitor circuit of claim 10 , wherein the pair of input sampling capacitors is a first pair of input sampling capacitors, and further comprising a second pair of input sampling capacitors coupled to the first pair of input sampling capacitors, wherein the switching circuit charges the first pair of input sampling capacitors from the differential input and charges the second pair of input sampling capacitors from the inputs of the differential amplifier in the first phase of the reference sampling clock, wherein the charging of the first pair of input sampling capacitors and the second pair of input sampling capacitors is referenced to a common-mode reference, so that amplifier offset appears across the second pair of input sampling capacitors, and wherein the switching circuit couples the second pair of input sampling capacitors in series with the amplifier inputs in the second phase of the reference sampling clock to remove amplifier offset, whereby the differential switched-capacitor circuit provides correlated double-sampling operation.
12 . The differential switched-capacitor circuit of claim 11 , wherein the chopping circuit includes:
a first pair of quads of chopping switches that differentially interchange connections between a first pair of the charge transfer switches that couple the second pair of input sampling capacitors to the pair of feedback capacitors during the first phase of the reference sampling clock; and
a second pair of quads of chopping switches that differentially interchange connections between a second pair of the charge transfer switches that couple the first pair of input sampling capacitors and the second pair of input sampling capacitors to the pair of feedback capacitors during the second phase of the reference sampling clock.
13 . The differential switched-capacitor circuit of claim 11 , wherein the chopping circuit includes:
a first quad of chopping switches that differentially interchanges connections between a first pair of the charge transfer switches that couple the second pair of input sampling capacitors to the pair of feedback capacitors during the first phase of the reference sampling clock;
a second quad of chopping switches that differentially interchanges connections between a second pair of the charge transfer switches that couple the first pair of input sampling capacitors and the second pair of input sampling capacitors to the pair of feedback capacitors during the second phase of the reference sampling clock; and
a third quad of chopping switches that differentially interchanges connections between the feedback capacitors and connections between the first quad of chopping switches and the second quad of chopping switches.
14 . The differential switched-capacitor circuit of claim 7 , wherein the chopping circuit includes a pair of quads of chopping switches that differentially interchange connections between the pair of input sampling capacitors and a pair of charge transfer switches of the switching circuit that transfer the charge from the pair of input sampling capacitors during the second phase of the reference sampling clock.
15 . The differential switched-capacitor circuit of claim 7 , wherein the chopping circuit includes a pair of quads of chopping switches that differentially interchange connections between the pair of input sampling capacitors and a pair of charge transfer switches that couple the pair of input sampling capacitors to a fixed voltage reference during a portion of the first phase of the reference sampling clock.
16 . A method of reducing DC offset due to charge injection asymmetry in a differential switched-capacitor circuit, the method comprising:
operating the differential switched-capacitor circuit to sample a differential input signal with a pair of input sampling capacitors at a reference sampling frequency, whereby the DC offset is caused by edges of a first control operating the differential switched-capacitor circuit at the reference sampling frequency coupling through one or more charge transfer switches of the differential switched-capacitor circuit and accumulating to produce the DC offset, wherein the differential switched-capacitor circuit is a differential switched-capacitor integrator or gain-stage including a pair of input sampling capacitors, wherein the one or more charge transfer switches alternatively charge the pair of input sampling capacitors from a differential input in a first phase of a reference sampling clock and transfer charge from the pair of input sampling capacitors in a second phase of the reference sampling clock to a pair of feedback capacitors coupled between outputs and inputs of a differential amplifier; and
chopping switching paths of each terminal of the one or more charge transfer switches to alternate connections of each terminal of the one or more charge transfer switches with a chopper operating at a chopping frequency different from the reference sampling frequency, wherein the chopper alternates connections to at least some of the one or more charge transfer switches between differential pairs of signals through the differential switched-capacitor circuit, whereby the chopper modulates the charge-injection of the one or more charge transfer switches away from DC.
17 . The method of claim 16 , wherein the reference sampling frequency is a multiple of the chopping frequency, whereby the chopper averages the charge injection in half-periods of the second frequency and effectively subtracts injected charge in consecutive half-periods.
18 . The method of claim 17 , wherein the reference sampling frequency is a multiple greater than or equal to 100 of the chopping frequency.
19 . The method of claim 16 , wherein the pair of input sampling capacitors is a first pair of input sampling capacitors, wherein the differential switched-capacitor integrator or gain-stage further includes a second pair of input sampling capacitors, and wherein the operating the differential switched-capacitor circuit comprises:
charging the first pair of input sampling capacitors from the differential input and charging the second pair of input sampling capacitors from the inputs of the differential amplifier during the first phase of the reference sampling clock, wherein the charging of the first pair of input sampling capacitors and the second pair of input sampling capacitors is referenced to a common-mode reference, so that amplifier offset appears across the second pair of input sampling capacitors; and
coupling the second pair of input sampling capacitors to the inputs of the differential amplifier in the second phase of the reference sampling clock to remove the amplifier offset, whereby the differential switched-capacitor circuit provides correlated double-sampling operation.
20 . The method of claim 19 , wherein the chopping switching paths comprises:
differentially interchanging connections between a first pair of the one or more charge transfer switches that couple the second pair of input sampling capacitors to the pair of feedback capacitors during the first phase of the reference clock with a first pair of quads of chopping switches; and
differentially interchanging connections between a second pair of the one or more charge transfer switches that couple the first pair of input sampling capacitors and the second pair of input sampling capacitors to the feedback capacitors during the second phase of the reference sampling clock with a second pair of quads of chopping switches.
21 . The method of claim 19 , wherein the chopping switching paths comprises:
differentially interchanging connections between each terminal of a first pair of the one or more charge transfer switches that couple the second pair of input sampling capacitors to the pair of feedback capacitors during the first phase of the reference clock with a first quad of chopping switches;
differentially interchanging connections between each terminal of a second pair of the one or more charge transfer switches that couple the first pair of input sampling capacitors and the second pair of input sampling capacitors to the pair of feedback capacitors during the second phase of the reference sampling clock with a second quad of chopping switches; and
differentially interchanging connections between the feedback capacitors and connections between the first quad of chopping switches and the second quad of chopping switches with a third quad of chopping switches.
22 . The method of claim 16 , wherein the chopping switching paths comprises differentially interchanging connections between the pair of input sampling capacitors and ones of the one or more charge transfer switches that transfer the charge from the pair of input sampling capacitors during the second phase of the reference sampling clock with a pair of quads of chopping switches.
23 . The method of claim 16 , wherein the chopping switching paths comprises differentially interchanging connections between the pair of input sampling capacitors and a pair of the one or more charge transfer switches that couple the pair of the input sampling capacitors to a fixed voltage reference during a portion of the first phase of the reference sampling clock.