Semiconductor structures and methods of manufacturing semiconductor structures
A semiconductor structure includes a region of semiconductor material of a first conductivity type. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device is in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region of the second conductivity type and anode region of the first conductivity type. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor device.
1 . A semiconductor structure, comprising:
a region of semiconductor material comprising a first conductivity type, a first side, and a second side opposite to the first side;
a first doped region comprising a second conductivity type opposite to the first conductivity type within the region of semiconductor material spaced apart from the first side at a first depth;
a semiconductor device comprising at least a first part in a first portion of the region of semiconductor material between the first doped region and the first side and comprising a first current carrying region of the second conductivity type and a second current carrying region; and
a PN diode in a second portion of the region of semiconductor material and comprising an anode region of the first conductivity type and cathode region of the second conductivity type;
wherein:
the anode region is coupled to the first current carrying region of the semiconductor device;
the cathode region is coupled to the first doped region; and
the first doped region is configured to suppress current injection from the semiconductor device into the region of semiconductor material below the first doped region in response to a forward bias applied between the first current carrying region and the second current carrying region.
2 . The semiconductor structure of claim 1 , wherein:
the semiconductor device comprises an LDMOS device;
the first current carrying region comprises a drain region;
the second current carrying region comprises the second conductivity type; and
the second current carrying region comprises a source region.
3 . The semiconductor structure of claim 2 , further comprising:
a double RESURF structure comprising:
a second doped region of the second conductivity type in the first portion of the region of semiconductor material; and
a third doped region of the first conductivity type interposed between the second doped region and the first doped region;
wherein:
the first current carrying region is within the second doped region.
4 . The semiconductor structure of claim 1 , further comprising:
a contact region in the region of semiconductor material coupling the cathode region to the first doped region.
5 . The semiconductor structure of claim 1 , wherein:
the first doped region comprises an ion-implanted region.
6 . The semiconductor structure of claim 1 , wherein:
the first depth is less than about 2.5 microns.
7 . The semiconductor structure of claim 1 , wherein:
the semiconductor device comprises a second PN diode; and
the second current carrying region comprises the first conductivity type.
8 . The semiconductor structure of claim 7 , further comprising:
a double RESURF structure comprising:
a second doped region of the second conductivity type in the first portion of the region of semiconductor material; and
a third doped region of the first conductivity type interposed between the second doped region and the first doped region;
wherein:
the first current carrying region is within the second doped region.
9 . The semiconductor structure of claim 1 , wherein:
the first doped region laterally extends across the first portion and the second portion of the region of semiconductor material.
10 . The semiconductor structure of claim 9 , further comprising:
a second doped region of the first conductivity type in the region of semiconductor material vertically interposed between the PN diode and the first doped region.
11 . A semiconductor structure, comprising:
a body of semiconductor material comprising a first conductivity type, a first side, and a second side opposite to the first side;
a first doped region within the body of semiconductor spaced apart from the first side and comprising a second conductivity type opposite the first conductivity type;
a first semiconductor device at least partially in a first portion of the body of semiconductor material between the first doped region and the first side and comprising:
a second doped region comprising the second conductivity type adjacent to the first side;
a first current carrying region comprising the second conductivity type within the second doped region;
a third doped region comprising the first conductivity type adjacent to the first side and laterally spaced apart from the second doped region;
a second current carrying region within the third doped region; and
a fourth doped region comprising the first conductivity type vertically interposed between the second doped region and the first doped region; and
a second semiconductor device in a second portion of the body of semiconductor material between the first doped region and the first side and comprising:
a fifth doped region comprising the first conductivity type; and
a sixth doped region comprising the second conductivity type;
wherein:
the fifth doped region and the sixth doped region comprise a first PN diode;
the fifth doped region is coupled to the first current carrying region; and
the sixth doped region is coupled to the first doped region.
12 . The semiconductor structure of claim 11 , wherein:
the second doped region and the fourth doped region comprise a double RESURF structure.
13 . The semiconductor structure of claim 11 , wherein:
the first semiconductor device comprises a double RESURF LDMOS device;
the first current carrying region comprises a drain region; and
the second current carrying region comprises a second conductivity type source region.
14 . The semiconductor structure of claim 11 , wherein:
the first semiconductor device comprises a second PN diode comprising a higher breakdown voltage than the first PN diode; and
the second current carrying region comprises the first conductivity type.
15 . The semiconductor structure of claim 11 , further comprising:
a contact region extending from the first side to the first doped region;
wherein:
the contact region couples the sixth doped region to the first doped region.
16 . The semiconductor structure of claim 11 , further comprising:
a seventh doped region of the first conductivity type vertically interposed between the second semiconductor device and the first doped region.
17 . A method for making a semiconductor structure, comprising:
providing a region of semiconductor material comprising a first conductivity type, a first side, and a second side opposite to the first side;
providing a first doped region comprising a second conductivity type opposite to the first conductivity type within the region of semiconductor material spaced apart from the first side at a first depth;
providing a semiconductor device comprising at least a first part in a first portion of the region of semiconductor material between the first doped region and the first side and comprising a first current carrying region of the second conductivity type and a second current carrying region; and
providing a PN diode in a second portion of the region of semiconductor material and comprising an anode region of the first conductivity type and a cathode region of the second conductivity type;
wherein:
the anode region is coupled to the first current carrying region of the semiconductor device;
the cathode region is coupled to the first doped region; and
the first doped region is configured to suppress current injection from the semiconductor device into the region of semiconductor material below the first doped region in response to a forward bias applied to the first current carrying region.
18 . The method of claim 17 , wherein:
providing the semiconductor device comprises providing an LDMOS device;
the first current carrying region comprises a drain region;
the second current carrying region comprises the second conductivity type; and
the second current carrying region comprises a source region.
19 . The method of claim 17 , further comprising:
providing a second doped region of the second conductivity type in the region of semiconductor material coupling the anode region to the first doped region.
20 . The method of claim 17 , wherein:
providing the region of semiconductor material comprises providing a semiconductor substrate with a semiconductor region;
the semiconductor region defines the first side; and
providing the first doped region comprises ion implanting the first doped region into the semiconductor region through the first side.