Methods and systems of current sensing in switching power converters

1. A method of operating a switching power converter, the method comprising:

discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle;

providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode;

charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode; and

providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode,

wherein providing the emulated signal further comprises:

sensing that the discharge mode has a duration shorting than a blanking time for measuring a voltage drop across the low-side FET; and responsive to the discharge mode having the duration shorter than the blanking time, and

providing a ramp signal to the voltage regulator, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode.

2. The method of claim 1 :

wherein providing the signal indicative of instantaneous current to the voltage regulator further comprising driving the signal indicative of instantaneous current to a first terminal of a power module; and

wherein providing the emulated signal further comprising driving the emulated signal to the first terminal of the power module.

3. The method of claim 1 wherein providing the emulated signal further comprises:

sensing that the buck converter is in a non-transient operation; and

providing, during the charge mode of the second cycle, a signal indicative of average current to the voltage regulator, the signal indicative of average current having a magnitude proportional to an average current through the inductor during at least a portion of the first cycle.

4. The method of claim 3 :

wherein providing the signal indicative of instantaneous current during the discharge mode further comprises sensing the voltage drop across the low-side FET, and driving the signal indicative of instantaneous current proportional to the voltage drop across the low-side FET; and

wherein providing the signal indicative of average current further comprises:

generating, during the first cycle, the signal indicative of average current through the inductor during the discharge mode; and

driving, during the charge mode of the second cycle, the signal indicative of average current.

5. The method of claim 3 wherein sensing that the buck converter is in the non-transient operation further comprises sensing that the discharge mode has the duration longer than the blanking time for measuring the voltage drop across the low-side FET.

6. The method of claim 1 wherein providing the emulated signal further comprises:

sensing that the buck converter is in transient operation.

7. The method of claim 6 wherein sensing that the buck converter is in the transient operation further comprises sensing that the discharge mode has the duration shorter than the blanking time for measuring the voltage drop across the low-side FET.

8. A power module comprising:

a switch-node terminal, a PWM-input terminal, and a monitor-output terminal;

a high-side FET defining a drain, a source coupled to the switch-node terminal, and a gate;

a low-side FET defining drain coupled to the switch-node terminal, a source, and a gate; and

a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM-input terminal, and the monitor-output terminal, the controller configured to:

responsive to de-assertion of the PWM-input terminal, make the high-side FET non-conductive and the low-side FET conductive to define a discharge mode in a first cycle;

drive, during the discharge mode, a signal indicative of instantaneous current to the monitor-output terminal, the signal indicative of instantaneous current directly proportional to voltage drop across the low-side FET during at least a portion of the discharge mode;

responsive to assertion of the PWM-input terminal, make the low-side FET non-conductive and the high-side FET conductive to define a charge mode in a second cycle subsequent to the first cycle; and

drive, during the charge mode of the second cycle, an emulated signal to the monitor-output terminal, the emulated signal generated based on the current through the low-side FET in the first cycle,

wherein when the controller drives the emulated signal to the monitor-output terminal, the controller is further configured to:

sense a non-transient operation; and

drive, during the charge mode of the second cycle, a signal indicative of average current to the monitor-output terminal, the signal indicative of average current having a magnitude proportional to an average current through the low-side FET during at least a portion of the first cycle.

9. The power module of claim 8 wherein when the controller drives the signal indicative of average current to the monitor-output terminal, the controller is further configured to:

generate, during the first cycle, an intermediate signal indicative of average current through low-side FET during the discharge mode; and

drive, during the charge mode of the second cycle, the signal indicative of average current based on the intermediate signal indicative of average current.

10. The power module of claim 8 wherein when the controller senses the non-transient operation, the controller is further configured to sense that the discharge mode has a duration longer than a blanking time for measuring a voltage drop across the low-side FET.

11. The power module of claim 8 wherein when the controller drives the emulated signal to the monitor-output terminal, the controller is further configured to:

sense a transient operation; and

drive, during the charge mode of the second cycle, a ramp signal to the monitor-output terminal, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode.

12. The power module of claim 11 wherein when the controller senses the transient operation, the controller is further configured to sense that the discharge mode has a duration shorter than a blanking time for measuring a voltage drop across the low-side FET.

13. A system comprising:

an inductor defining a first lead and a second lead coupled to a load;

a voltage regulator defining a voltage-monitor input coupled to the second lead, a PWM output, and a current-monitor input; and

a power module defining a switch node coupled to the first lead, a PWM input coupled to the PWM output, and a monitor output coupled to the current-monitor input, the power module comprising:

a high-side FET defining a source coupled to the switch node and a gate;

a low-side FET defining drain coupled to the switch node, and a gate; and

a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM input, and the current-monitor input of the voltage regulator, the controller configured to:

responsive to de-assertion of the PWM input, make the high-side FET non-conductive and the low-side FET conductive to discharge the inductor during a discharge mode of a first cycle;

drive, during the discharge mode, a signal indicative of instantaneous current to the current-monitor input, the signal indicative of instantaneous current proportional to an instantaneous current through the inductor during at least a portion of the discharge mode;

responsive to assertion of the PWM input, make the low-side FET non-conductive and the high-side FET conductive to charge the inductor during a charge mode of a second cycle subsequent to the first cycle; and

drive, during the charge mode of the second cycle, an emulated signal to the current-monitor input, the emulated signal generated based on a current through the inductor in the first cycle,

wherein when the controller drives the emulated signal to the current-monitor input, the controller is further configured to:

sense a transient operation of the system; and

drive, during the charge mode of the second cycle, a ramp signal to the current-monitor input, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode of the first cycle.

14. The system of claim 13 wherein when the controller drives the emulated signal to the current-monitor input, the controller is further configured to:

sense a non-transient operation of the system; and

drive, during the charge mode of the second cycle, a signal indicative of average current to the current-monitor input, the signal indicative of average current having a magnitude proportional to an average current through the inductor during at least a portion of the first cycle.

15. The system of claim 14 :

wherein when the controller drives the signal indicative of instantaneous current to the current-monitor input, the controller is further configured to sense a voltage drop across the low-side FET, and drive the signal indicative of instantaneous current proportional to the voltage drop across the low-side FET; and

wherein when the controller drives the signal indicative of average current to the current-monitor input, the controller is further configured to:

generate an intermediate signal indicative of average current through the inductor during the discharge mode of the first cycle; and

drive, during the charge mode of the second cycle, the signal indicative of average current based on the intermediate signal indicative of average current.

16. The system of claim 14 wherein when the controller senses the non-transient operation, the controller is further configured to sense that the discharge mode has a duration longer than a blanking time for measuring voltage drop across the low-side FET.

17. The system of claim 13 wherein when the controller senses the transient operation, the controller is further configured to sense that the discharge mode has a duration shorter than a blanking time for measuring voltage drop across the low-side FET.