Measuring device defect sensitization in transistor-level circuits
A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.
1. A method of determining defect sensitization, the method comprising:
parsing a netlist of a circuit design to determine a plurality of potential defects;
partitioning the circuit design into a plurality of blocks;
generating, based on the plurality of blocks, a graph representing the circuit design;
determining a transitive closure of the graph indicating reachability relationships among the plurality of blocks;
grouping the plurality of potential defects based on the reachability relationships among the plurality of blocks indicated by the transitive closure of the graph to produce a plurality of groups of potential defects;
selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects;
simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks; and
determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.
2. The method of claim 1 , wherein partitioning the circuit design into a plurality of blocks comprises:
identifying a plurality of power-nets in the circuit design; and
disconnecting the circuit design at a portion of the plurality of power-nets to form the plurality of blocks.
3. The method of claim 1 , wherein the graph is a directed graph, and wherein each node of the directed graph is a block of the plurality of blocks.
4. The method of claim 1 , wherein an edge in the graph indicates a direction of signal propagation in the circuit design.
5. The method of claim 1 , further comprising:
probing an input port and output port of each node in the graph; and
simulating the circuit design to produce a plurality of waveforms for the input port and the output port of each node in the graph.
6. The method of claim 5 , wherein determining the defect sensitization comprises comparing the plurality of waveforms to the set of outputs of the plurality of blocks.
7. The method of claim 6 , wherein comparing the plurality of waveforms to the set of outputs of the plurality of blocks comprises:
calculating an absolute difference between the plurality of waveforms and the set of outputs of the plurality of blocks time-point by time-point;
integrating the absolute difference to produce a value; and
dividing the value by a total transient time.
8. The method of claim 1 , wherein potential defects in a first group of the plurality of groups of potential defects have no effect on sensitization of potential defects in a second group of the plurality of groups of potential defects different from the first group.