IP Library › Granted Patent US 11,935,794
Granted Patent B2
US 11,935,794 · App. 18/079,053 · Granted Mar 19, 2024

Method for forming long channel back-side power rail device

Inventors: Huan-Chieh Su (Tianzhong Township, TW); Cheng-Chi Chuang (New Taipei, TW); Chih-Hao Wang (Baoshan Township, TW); Zhi-Chang Lin (Zhubei, TW); Li-Zhen Yu (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/823431H01L21/823412H01L29/6681H01L29/785H01L2029/7858
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Quick Facts
Patent No.
US 11,935,794
App. No.
18/079,053
Granted
Mar 19, 2024
Kind
B2
Abstract

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Claims (56)

1. A method of forming a semiconductor transistor device, the method comprising:

forming a channel structure over a substrate;

forming a first source/drain structure and a second source/drain structure on opposite sides of the channel structure;

forming a gate structure surrounding the channel structure;

forming a back-side capping trench from a back-side of the substrate; and

forming a back-side dielectric cap in the back-side capping trench.

2. The method of claim 1 , wherein a protective spacer is formed along sidewalls of the first source/drain structure and the second source/drain structure from a remaining portion of the substrate when forming the back-side capping trench.

3. The method of claim 2 , further comprising forming an etch stop layer on the substrate prior to forming the channel structure.

4. The method of claim 3 , further comprising forming a sacrificial source/drain contact through the etch stop layer in the substrate on one side of the channel structure prior to forming the first source/drain structure and the second source/drain structure.

5. The method of claim 4 , wherein the protective spacer is formed covering a lower sidewall of the first source/drain structure connecting the sacrificial source/drain contact.

6. The method of claim 4 , further comprising:

removing the sacrificial source/drain contact from a back-side contact trench and recessing the first source/drain structure exposed to the back-side contact trench after forming the back-side dielectric cap; and

filling a back-side source/drain contact in the back-side contact trench contacting the first source/drain structure;

wherein the protective spacer is removed when recessing the first source/drain structure.

7. The method of claim 4 , further comprising:

forming a hard mask covering a top surface of the sacrificial source/drain contact after flipping the substrate;

wherein the substrate is partially removed with the hard mask in place.

8. The method of claim 7 , further comprising:

forming a sidewall liner along a sidewall of the sacrificial source/drain contact;

recessing a bottom surface of the second source/drain structure with the sidewall liner and the protective spacer in place.

9. The method of claim 2 , wherein the protective spacer is formed extending along a bottom surface of the gate structure.

10. The method of claim 1 , wherein forming the channel structure comprises:

forming a fin structure by stacking first semiconductor layers and second semiconductor layers alternately over the substrate;

forming a dummy gate structure over the fin structure;

removing a portion of the fin structure uncovered by the dummy gate structure; and

replacing the dummy gate structure and the first semiconductor layers with the gate structure.

11. A method of forming a semiconductor transistor device, the method comprising:

forming a channel structure over a substrate;

forming a sacrificial source/drain contact in the substrate on one side of the channel structure;

forming a first source/drain structure and a second source/drain structure on opposite sides of the channel structure, the first source/drain structure overlying the sacrificial source/drain contact;

forming a gate structure surrounding the channel structure;

forming a back-side capping trench to expose a bottom surface of the gate structure and a bottom surface of the second source/drain structure, wherein the bottom surface of the second source/drain structure is recessed; and

forming a back-side dielectric cap in the back-side capping trench.

12. The method of claim 11 , wherein forming the back-side capping trench comprises partially removing the substrate to expose a sidewall surface of the sacrificial source/drain contact while leaving a portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer.

13. The method of claim 12 , wherein the substrate is removed by an isotropic etch process that exposes the bottom surface of the gate structure while leaving the protective spacer at a corner of the first source/drain structure.

14. The method of claim 12 , further comprising:

forming a sidewall liner covering the sidewall surface of the sacrificial source/drain contact;

wherein the back-side capping trench is formed with the sidewall liner in place.

15. The method of claim 11 , further comprising replacing the sacrificial source/drain contact by a back-side source/drain contact under and contacting the first source/drain structure after forming the back-side dielectric cap.

16. The method of claim 11 , wherein forming the channel structure comprises:

forming a fin structure by stacking first semiconductor layers and second semiconductor layers alternately over the substrate;

forming a dummy gate structure over the fin structure;

removing a portion of the fin structure uncovered by the dummy gate structure;

forming inner spacers on opposite sides of remaining portions of the first semiconductor layers; and

replacing the dummy gate structure and the first semiconductor layers with the gate structure.

17. A semiconductor device, comprising:

a channel structure;

a gate structure wrapping around the channel structure;

a first source/drain structure and a second source/drain structure disposed on opposite sides of the channel structure; and

a back-side dielectric cap disposed under and extended along the second source/drain structure and the gate structure;

wherein the first source/drain structure has a bottom surface with a concave shape.

18. The semiconductor device of claim 17 , further comprising:

a back-side source/drain contact disposed under and contacting the first source/drain structure; and

wherein the back-side source/drain contact comprises a ledge extended under the gate structure.

19. The semiconductor device of claim 18 , wherein the back-side source/drain contact has a top surface locating higher than a bottom surface of the gate structure.

20. The semiconductor device of claim 17 , wherein a bottom surface of the second source/drain structure has a concave shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2022
From: SU, HUAN-CHIEH; CHUANG, CHENG-CHI; WANG, CHIH-HAO; LIN, ZHI-CHANG; YU, LI-ZHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 062049/0958 →
Continuity (3)
Continuation 17068037 · Oct 12, 2020
Provisional Application 63021740 · May 8, 2020
Related Publication 20230106478A1 · Apr 6, 2023