Data decoding method and device in communication and broadcast system
The present disclosure relates to a communication method and system for converging a 5 th -Generation (5G) communication system for supporting higher data rates beyond a 4 th -Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Further, the present disclosure relates to decoding of a turbo code in a communication system including long term evolution (LTE), and to efficiently implement a method, procedure, and device for receiving and decoding a signal transmitted in a mobile communication system.
1. A method performed by a first device of a communication system comprising:
obtaining an estimated bit sequence based on signals received from a second device;
based on a decoding of the estimated bit sequence being unsuccessful, determining whether a specified condition for a code dimension is satisfied or not, the code dimension indicating a length of the estimated bit sequence;
based on the specified condition being satisfied, obtaining a modified bit sequence by inverting one bit in the estimated bit sequence, wherein a position of the one bit in the estimated bit sequence to be inverted is determined by the code dimension; and
performing a cyclic redundancy check (CRC) for the modified bit sequence.
2. The method of claim 1 ,
wherein, in a case that the one bit in the estimated bit sequence is 1, the one bit is converted to 0, and
wherein, in a case that the one bit in the estimated bit sequence is 0, the one bit is converted to 1.
3. The method of claim 1 , wherein the specified condition indicates that the code dimension is one of specified values.
4. The method of claim 1 , wherein the specified condition indicates that the code dimension is one of specified values and a code rate is greater than a specified threshold.
5. The method of claim 4 ,
wherein the specified values include at least one of 48, 72, 80, 88, 120, 160, 208, or a combination thereof, and
wherein the specified threshold is substantially 0.75.
6. The method of claim 1 , wherein the specified condition indicates that the code dimension is one of specified values and a code length is smaller than a specified threshold.
7. The method of claim 6 ,
wherein the estimated bit sequence is obtained based on a turbo coding system using the code dimension and a code length, and
wherein the code length indicates a length of codeword bit sequence of the signals.
8. The method of claim 6 , wherein the specified values include at least one of 48, 72, 80, 88, 120, 160, 208, or a combination thereof.
9. The method of claim 1 ,
wherein the position of the one bit is indicated by one bit index,
wherein the one bit index is 40 based on the code dimension being 48,
wherein the one bit index is 57 based on the code dimension being 72,
wherein the one bit index is 72 based on the code dimension being 80,
wherein the one bit index is 66 based on the code dimension being 88,
wherein the one bit index is 105 based on the code dimension being 120,
wherein the one bit index is 152 based on the code dimension being 160, and
wherein the one bit index is 200 based on the code dimension being 208.
10. A first device of a communication system comprising:
at least one processor; and
memory storing instructions that, when executed by the at least one processor, cause the first device to:
obtain an estimated bit sequence based on signals received from a second device,
based on a decoding of the estimated bit sequence being unsuccessful, determine whether a specified condition for a code dimension is satisfied or not, the code dimension indicating a length of the estimated bit sequence,
based on the specified condition being satisfied, obtain a modified bit sequence by inverting one bit in the estimated bit sequence, wherein a position of the one bit in the estimated bit sequence to be inverted is determined by the code dimension, and
perform a cyclic redundancy check (CRC) for the modified bit sequence.
11. The first device according to claim 10 ,
wherein, in a case that the one bit in the estimated bit sequence is 1, the one bit is converted to 0, and
wherein, in a case that the one bit in the estimated bit sequence is 0, the one bit is converted to 1.
12. The first device according to claim 10 , wherein the specified condition indicates that the code dimension is one of the preset values.
13. The first device according to claim 10 , wherein the specified condition indicates that the code dimension is one of preset values and a code rate is greater than a specified threshold.
14. The first device according to claim 13 ,
wherein the preset values include at least one of 48, 72, 80, 88, 120, 160, 208, or a combination thereof, and
wherein the specified threshold is substantially 0.75.
15. The first device according to claim 10 , wherein the specified condition indicates that the code dimension is one of preset values and a code length is smaller than a specified threshold.
16. The first device according to claim 15 ,
wherein the estimated bit sequence is obtained based on a turbo coding system using the code dimension and a code length, and
wherein the code length indicates a length of codeword bit sequence of the signals.
17. The first device according to claim 15 , wherein the preset values include at least one of 48, 72, 80, 88, 120, 160, 208, or a combination thereof.
18. The first device according to claim 10 ,
wherein the position of the one bit is indicated by one bit index,
wherein the one bit index is 40 based on the code dimension being 48,
wherein the one bit index is 57 based on the code dimension being 72,
wherein the one bit index is 72 based on the code dimension being 80,
wherein the one bit index is 66 based on the code dimension being 88,
wherein the one bit index is 105 based on the code dimension being 120,
wherein the one bit index is 152 based on the code dimension being 160, and
wherein the one bit index is 200 based on the code dimension being 208.
19. A non-transitory computer-readable storage medium comprising memory storing instructions that, when executed by a processor, cause a first electronic device to perform operations including:
obtaining an estimated bit sequence based on signals received from a second device,
based on a decoding of the estimated bit sequence being unsuccessful, determining whether a specified condition for a code dimension is satisfied or not, the code dimension indicating a length of the estimated bit sequence,
based on the specified condition being satisfied, obtaining a modified bit sequence by inverting one bit in the estimated bit sequence, and
performing a cyclic redundancy check (CRC) for the modified bit sequence,
wherein a position of the one bit in the estimated bit sequence to be inverted is determined by the code dimension.