Integrated circuit and memory device including sampling circuit
An integrated circuit includes a sampling control circuit configured to: generate a counting signal according to a periodic signal during a sampling period, and generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal; and a sampling circuit configured to: store an input address as a plurality of sampling addresses according to the respective sampling enable signals, and generate a plurality of valid section signals based on the sampling enable signals to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated valid section signals.
1. An integrated circuit comprising:
a sampling control circuit configured to:
generate a counting signal according to a periodic signal during a sampling period, and
generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal; and
a sampling circuit configured to:
store an input address as a plurality of sampling addresses according to the respective sampling enable signals, and
generate a plurality of valid section signals which are activated based on the respective sampling enable signals to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated valid section signals.
2. The integrated circuit of claim 1 , wherein the sampling control circuit is configured to generate the sampling enable signals by comparing the random bits with the counting bits, numbers to be compared between the random bits and the counting bits being different for the respective sampling enable signals during the sampling period.
3. The integrated circuit of claim 1 , wherein the sampling control circuit includes:
an oscillator configured to generate the periodic signal;
a counter configured to generate the counting signal by counting a toggling number of the periodic signal according to a sampling signal defining the sampling period;
a variable bit comparison circuit configured to generate a plurality of match signals by varying numbers of the random bits and the counting bits, which are to be compared with each other for the respective match signals; and
a control signal generation circuit configured to output the sampling enable signals set to a first logic level in response to the sampling signal and to a second logic level in response to the respective match signals.
4. The integrated circuit of claim 3 ,
wherein the variable bit comparison circuit includes a plurality of comparators configured to output the respective match signals, and
wherein each of the comparators is configured to generate a corresponding match signal by comparing the numbers with each other between the random bits and the counting bits, each of the numbers corresponding to the comparator being more than a comparator at a previous stage.
5. The integrated circuit of claim 3 ,
wherein the control signal generation circuit includes a plurality of latch circuits, and
wherein each of the latch circuits is configured to:
receive the sampling signal as a set signal,
receive, as a reset signal, an inverted signal of a corresponding match signal, and
output a corresponding sampling enable signal.
6. The integrated circuit of claim 1 , wherein the sampling circuit includes:
a section definition circuit configured to generate the valid section signals set to a first logic level according to the respective sampling enable signals and to a second logic level according to a sampling signal;
an address storing circuit configured to store the input address as the sampling addresses according to the sampling enable signals; and
an address output circuit configured to output one of the sampling addresses as the target address according to the uppermost valid section signal, when the sampling signal is inputted.
7. The integrated circuit of claim 6 , wherein the section definition circuit includes:
an edge detection circuit configured to generate a plurality of falling edge signals by detecting falling edges of the respective sampling enable signals; and
a valid signal generation circuit configured to output the valid section signals set to a first logic level according to the respective falling edge signals and to a second logic level according to an inverted signal of the sampling signal.
8. The integrated circuit of claim 6 , wherein the address output circuit includes:
an output control circuit configured to generate a plurality of output enable signals based on the respective valid section signals, when the sampling signal is inputted, an output enable signal corresponding to the uppermost valid section signal being activated among the output enable signals; and
a target output circuit configured to output one of the sampling addresses as the target address according to the output enable signals.
9. The integrated circuit of claim 8 ,
wherein the output control circuit includes a plurality of output controllers configured to generate the respective output enable signals, and
wherein each of the output controllers includes logic gates for performing a logic AND operation on the sampling signal, a corresponding valid section signal, and inverted signals of upper valid section signals.
10. The integrated circuit of claim 1 , further comprising a random signal generation circuit configured to generate the random signal according to a sampling signal.
11. The integrated circuit of claim 10 , wherein the random signal generation circuit includes a pseudo-random number generator (PRNG) based on a linear feedback shift register (LFSR).
12. A memory device comprising:
a sampling control circuit configured to:
generate a counting signal according to a target refresh command, and
generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal;
an address storing circuit configured to store an input address as a plurality of sampling addresses according to the respective sampling enable signals;
an address output circuit configured to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated ones of a plurality of valid section signals which are activated based on the respective sampling enable signals, when the target refresh command is inputted; and
a row control circuit configured to refresh at least one word line corresponding to the target address in response to the target refresh command.
13. The memory device of claim 12 , wherein the sampling control circuit includes:
an oscillator configured to generate a periodic signal;
a counter configured to generate the counting signal by counting a toggling number of the periodic signal according to the target refresh command;
a variable bit comparison circuit configured to generate a plurality of match signals by varying numbers of the random bits and the counting bits, which are to be compared with each other for the respective match signals; and
a control signal generation circuit configured to output the sampling enable signals set to a first logic level in response to the target refresh command and to a second logic level in response to the respective match signals.
14. The memory device of claim 13 ,
wherein the variable bit comparison circuit includes a plurality of comparators configured to output the respective match signals, and
wherein each comparator is configured to generate a corresponding match signal by comparing the numbers with each other between the random bits and the counting bits, each of the numbers corresponding to the comparator being more than a comparator at a previous stage.
15. The memory device of claim 12 , further comprising a section definition circuit configured to generate the valid section signals set to a first logic level according to the respective sampling enable signals and to a second logic level according to the target refresh command.
16. The memory device of claim 15 , wherein the section definition circuit includes:
an edge detection circuit configured to generate a plurality of falling edge signals by detecting falling edges of the respective sampling enable signals; and
a valid signal generation circuit configured to output the valid section signals set to a first logic level according to the respective falling edge signals and to a second logic level according to an inverted signal of the target refresh command.
17. The memory device of claim 12 , wherein the address output circuit includes:
an output control circuit configured to generate a plurality of output enable signals based on the respective valid section signals, when the target refresh command is inputted, an output enable signal corresponding to the uppermost valid section signal being activated among the output enable signals; and
a target output circuit configured to output one of the sampling addresses as the target address according to the output enable signals.
18. The memory device of claim 17 ,
wherein the output control circuit includes a plurality of output controllers configured to generate the respective output enable signals, and
wherein each output controller includes logic gates for performing a logic AND operation on the target refresh command, a corresponding valid section signal, and inverted signals of upper valid section signals.
19. The memory device of claim 12 , further comprising a random signal generation circuit configured to generate the random signal according to the target refresh command.
20. A sampling method of an integrated circuit, comprising:
setting a random signal and generating a plurality of sampling enable signals, when a sampling period starts;
generating a counting signal by counting a toggling number of a periodic signal;
sequentially deactivating the sampling enable signals by comparing counting bits of the counting signal with random bits of the random signal;
storing an input address as a plurality of sampling addresses and sequentially activating a plurality of valid section signals, according to the deactivating of the sampling enable signals; and
outputting one of the sampling addresses as a target address according to an uppermost valid section signal among the activated valid section signals, when the sampling period ends.
21. The sampling method of claim 20 , wherein the sampling enable signals are sequentially deactivated by comparing the random bits with the counting bits, numbers to be compared between the random bits and the counting bits being different for the respective sampling enable signals.
22. The sampling method of claim 20 , wherein the sequentially deactivating the sampling enable signals includes:
deactivating a first sampling enable signal when a first bit among the random bits is the same as a first bit among the counting bits; and
deactivating a second sampling enable signal when first and second bits among the random bits are respectively the same as first and second bits among the counting bits.
23. The sampling method of claim 20 , further comprising deactivating the valid section signals when the sampling period ends.
24. A memory device comprising:
a refresh circuit configured to refresh a memory cell group corresponding to a target address;
a control circuit configured to generate N number of control signals each becoming disabled when a corresponding one of N number of pairs has an identical value, each of the pairs being of one or more bits from a N-bit count code and one or more bits from a N-bit random code and the pairs respectively having bitwise different ranges between one (1) bit and N bits; and
a sampling circuit configured to:
generate, based on an active address, N number of sample addresses when the control signals become disabled, respectively,
generate N number of section signals enabled when the control signals become disabled, respectively, and
select, as the target address, one of the sample addresses, the selected sample address corresponding to a last enabled one of the section signals.