Non-volatile static random access memory bit cells with ferroelectric field-effect transistors
Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.
1. A structure comprising:
a static random access memory bit cell including a first node and a second node;
a first ferroelectric field-effect transistor including a first gate terminal and a first source/drain terminal, the first gate terminal connected to the first node;
a second ferroelectric field-effect transistor including a second gate terminal and a second source/drain terminal, the second gate terminal connected to the second node; and
a signal line connected to the first source/drain terminal of the first ferroelectric field-effect transistor by a first unswitched line and to the second source/drain terminal of the second ferroelectric field-effect transistor by a second unswitched line.
2. A structure comprising:
a static random access memory bit cell including a first node and a second node;
a first ferroelectric field-effect transistor including a first gate terminal and a first source/drain terminal, the first gate terminal connected to the first node;
a second ferroelectric field-effect transistor including a second gate terminal and a second source/drain terminal, the second gate terminal connected to the second node; and
a signal line connected to the first source/drain terminal of the first ferroelectric field-effect transistor and to the second source/drain terminal of the second ferroelectric field-effect transistor,
wherein the first source/drain terminal of the first ferroelectric field-effect transistor is directly connected to the signal line, and the second source/drain terminal of the second ferroelectric field-effect transistor is directly connected to the signal line.
3. The structure of claim 2 wherein the first gate terminal includes a first ferroelectric layer, and the second gate terminal includes a second ferroelectric layer.
4. The structure of claim 2 wherein the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are n-type ferroelectric field-effect transistors.
5. The structure of claim 2 wherein the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are p-type ferroelectric field-effect transistors.
6. The structure of claim 1 wherein the static random access memory bit cell includes a first inverter and a second inverter that is cross-connected to the first inverter.
7. The structure of claim 1 wherein the static random access memory bit cell further comprises a first access transistor and a second access transistor, and further comprising:
a first bit line connected by the first access transistor to the first node; and
a second bit line connected by the second access transistor to the second node.
8. A method comprising:
forming a first ferroelectric field-effect transistor including a first gate terminal and a first source/drain terminal, wherein the first gate terminal is connected to a first node of a static random access memory bit cell;
forming a second ferroelectric field-effect transistor including a second gate terminal and a second source/drain terminal, wherein the second gate terminal is connected to a second node of the static random access memory bit cell; and
forming a signal line connected to the first source/drain terminal of the first ferroelectric field-effect transistor by a first unswitched line and to the second source/drain terminal of the second ferroelectric field-effect transistor by a second unswitched line.
9. The structure of claim 1 wherein the first gate terminal includes a first ferroelectric layer, and the second gate terminal includes a second ferroelectric layer.
10. The structure of claim 9 wherein the first ferroelectric layer and the second ferroelectric layer comprise a high-k dielectric material.
11. The structure of claim 1 wherein the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are n-type ferroelectric field-effect transistors.
12. The structure of claim 1 wherein the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are p-type ferroelectric field-effect transistors.
13. The structure of claim 1 wherein the signal line is configured to supply a programming voltage for a store operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.
14. The structure of claim 1 wherein the signal line is configured to supply a programming voltage for a restore operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.
15. The structure of claim 2 wherein the signal line is configured to supply a programming voltage for a store operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.
16. The structure of claim 2 wherein the signal line is configured to supply a programming voltage for a restore operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.
17. The structure of claim 2 wherein the static random access memory bit cell includes a first inverter and a second inverter that is cross-connected to the first inverter.
18. The structure of claim 2 wherein the static random access memory bit cell further comprises a first access transistor and a second access transistor, and further comprising:
a first bit line connected by the first access transistor to the first node; and
a second bit line connected by the second access transistor to the second node.
19. The method of claim 8 wherein the signal line is configured to supply a programming voltage for a store operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.
20. The method of claim 8 wherein the signal line is configured to supply a programming voltage for a restore operation to the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor.