Three-dimensional memory devices and fabricating methods thereof
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device can comprise a first semiconductor structure including a core region, a staircase region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure can include a memory stack on an activated semiconductor layer in the core region, a staircase structure on a supplemental semiconductor layer in the staircase region, and a first periphery circuit on a doped semiconductor film in the periphery region. The second semiconductor structure is connected with the first semiconductor structure.
1 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure including a core region, a staircase region, and a periphery region, comprising:
a memory stack on an activated semiconductor layer in the core region,
a staircase structure on a supplemental semiconductor layer in the staircase region, and
a first periphery circuit on an initial semiconductor layer in the periphery region; and
a second semiconductor structure including a second periphery circuit on a substrate;
wherein the second semiconductor structure is connected with the first semiconductor structure, and the first periphery circuit is located between the second periphery circuit and a lateral plane in which a surface of the supplemental semiconductor layer is located;
wherein the initial semiconductor layer, the activated semiconductor layer and the supplemental semiconductor layer are substantially coplanar in a lateral plane.
2 . The 3D memory device of claim 1 , wherein the first semiconductor structure further comprises:
a plurality of channel structures penetrating the memory stack in the core region, each channel structure including a functional layer and a semiconductor channel.
3 . The 3D memory device of claim 2 , wherein the first semiconductor structure further comprises:
a plurality of dummy channel structures penetrating the staircase structure in the staircase region; and
at least one slit structure vertically penetrating the memory stack and extending in a lateral direction to separate the plurality of channel structures.
4 . The 3D memory device of claim 3 , wherein the memory stack comprises:
a plurality of interleaved stack dielectric layers and stack gate structures stacked in a vertical direction.
5 . The 3D memory device of claim 4 , wherein the first semiconductor structure further comprises:
a plurality of contact structures including a plurality of channel structure contact structures in the core region, a plurality of word line contact structures in the staircase region, and a plurality of periphery contact structures in the periphery region; and
a plurality of first interconnect contact structures connected with corresponding contact structures, respectively.
6 . The 3D memory device of claim 5 , wherein the first periphery circuit comprises:
a high voltage circuit including a plurality of high voltage transistors on the initial semiconductor layer in the periphery region.
7 . The 3D memory device of claim 6 , wherein the first periphery circuit further comprises:
a low voltage circuit including a plurality of low voltage transistors on the initial semiconductor layer in the periphery region.
8 . The 3D memory device of claim 6 , wherein the second periphery circuit comprises:
a low low voltage circuit including a plurality of low low voltage transistors on the substrate; and
a plurality of second interconnect contact structures connected with corresponding low low voltage transistors, respectively.
9 . The 3D memory device of claim 8 , wherein the second periphery circuit further comprises:
a low voltage circuit including a plurality of low voltage transistors on the substrate.
10 . The 3D memory device of claim 8 , wherein:
the second semiconductor structure and the first semiconductor structure are connected in a face-to-face manner, such that the first interconnect contact structures and corresponding second interconnect contact structures are connected respectively at a bonding interface.
11 . The 3D memory device of claim 6 , wherein the first semiconductor structure further comprises:
a semiconductor film on the activated semiconductor layer, the supplemental semiconductor layer, and the initial semiconductor layer and including single crystalline silicon; and
the activated semiconductor layer comprises doped polycrystalline silicon.
12 . The 3D memory device of claim 11 , wherein:
the plurality of channel structures and the plurality of dummy channel structures penetrate through the semiconductor film; and
the high voltage transistors are formed partially in the semiconductor film.
13 . The 3D memory device of claim 11 , wherein the first semiconductor structure further comprises:
a spacer structure configured to separate a first portion of the semiconductor film in the periphery region and a second portion of the semiconductor film in the staircase region and the core region.
14 . The 3D memory device of claim 2 , wherein:
the functional layer of each channel structure comprises a blocking layer, a storage layer, and a tunneling layer; and
the semiconductor channel comprises a doped semiconductor channel region contacting the activated semiconductor layer.
15 . The 3D memory device of claim 1 , wherein the first semiconductor structure further comprises a pad layer on the activated semiconductor layer and the supplemental semiconductor layer.
16 . The 3D memory device of claim 15 , wherein the pad layer comprises:
a pad dielectric layer on the activated semiconductor layer, the supplemental semiconductor layer, and the initial semiconductor layer;
a plurality of pad structures embedded in the pad dielectric layer;
a wiring layer on the pad dielectric layer in the activated semiconductor layer and the supplemental semiconductor layer to connect with the plurality of pad structures; and
a protection layer to cover the wiring layer.
17 . A memory system, comprising:
a memory device configured to store data, and comprising:
a first semiconductor structure including a core region, a staircase region, and a periphery region, comprising:
a memory stack including an array of memory cells on an activated semiconductor layer in the core region,
a staircase structure on a supplemental semiconductor layer in the staircase region, and
a first periphery circuit on an initial semiconductor layer in the periphery region;
a second semiconductor structure including a second periphery circuit on a substrate, wherein the second semiconductor structure is connected with the first semiconductor structure, and the first periphery circuit is located between the second periphery circuit and a lateral plane in which a surface of the supplemental semiconductor layer is located, wherein the initial semiconductor layer, the activated semiconductor layer and the supplemental semiconductor layer are substantially coplanar in a lateral plane; and
a memory controller coupled to the memory device and configured to control the array of memory cells through the first peripheral circuit and the second periphery circuit.
18 . The memory system of claim 17 , wherein:
the first periphery circuit comprises a high voltage circuit including a plurality of high voltage transistors on the initial semiconductor layer in the periphery region;
the second periphery circuit comprises a low low voltage circuit including a plurality of low low voltage transistors on the substrate; and
the first periphery circuit or the second periphery circuit further comprises a low voltage circuit including a plurality of low voltage transistors on the initial semiconductor layer in the periphery region.
19 . The memory system of claim 18 , wherein the first semiconductor structure further comprises:
a semiconductor film on the activated semiconductor layer, the supplemental semiconductor layer, and the initial semiconductor layer and including single crystalline silicon; and
the activated semiconductor layer comprises doped polycrystalline silicon.
20 . The memory system of claim 19 , wherein:
a plurality of channel structures and a plurality of dummy channel structures penetrate through the semiconductor film; and
the high voltage transistors are formed partially in the semiconductor film.