Granted Patent B2

US 12,727,489 · App. 18/082,238 · Granted Sep 1, 2026

Inventors: Thorsten Scharf (Lappersdorf, DE); Josef Höglauer (Kirchheim-Heimstetten, DE); Angela Kessler (Sinzing, DE); Claus Waechter (Sinzing, DE)

Assignee: Infineon Technologies AG

H10W70/421H10W70/451H10W74/111H10W90/00

Abstract

Claims (44)

1 . A semiconductor device, comprising:

a premolded leadframe, comprising a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface; and

a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe, wherein the semiconductor package comprises a semiconductor chip and at least one electrical contact,

wherein surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush,

wherein the premolded leadframe comprises:

an electrically conductive plate that is formed from a metal or a metal alloy; and regions of electrically insulating mold material,

wherein the regions of electrically insulating mold material are arranged within openings that extend completely through a thinner part of the electrically conductive plate.

2 . The semiconductor device of claim 1 , wherein:

the premolded leadframe comprises a cavity,

the at least one electrical contact of the premolded leadframe forms at least a portion of a sidewall of the cavity, and

the semiconductor package is arranged in the cavity.

3 . The semiconductor device of claim 1 , wherein the electrical contacts of the premolded leadframe and the semiconductor package are configured to mechanically and electrically couple the semiconductor device to a printed circuit board.

4 . The semiconductor device of claim 1 , wherein the semiconductor package comprises a laminate material and the semiconductor chip is encapsulated in the laminate material.

5 . The semiconductor device of claim 1 , wherein the semiconductor package comprises a mold compound and the semiconductor chip is encapsulated in the mold compound.

6 . The semiconductor device of claim 1 , further comprising:

a further semiconductor chip, wherein the further semiconductor chip is encapsulated in the semiconductor package or in a further semiconductor package arranged on the main surface.

7 . The semiconductor device of claim 6 , wherein each of the semiconductor chip and the further semiconductor chip comprise a power transistor.

8 . The semiconductor device of claim 7 , wherein the power transistors form a high side switch and a low side switch of a half bridge circuit.

9 . The semiconductor device of claim 8 , wherein:

the semiconductor device is configured to operate as a DC-DC converter, and

the half bridge circuit is part of the DC-DC converter.

10 . The semiconductor device of claim 7 , wherein the premolded leadframe comprises a portion extending in a lateral direction, wherein the portion is configured to carry an electric current output by at least one of the power transistors.

11 . The semiconductor device of claim 1 , wherein the premolded leadframe comprises an electrical redistribution layer arranged on the opposite main surface of the premolded leadframe.

12 . The semiconductor device of claim 11 , wherein the electrical redistribution layer is configured for a routing of logical signals.

13 . The semiconductor device of claim 1 , further comprising:

a logic semiconductor chip configured to drive and/or control at least the semiconductor chip.

14 . The semiconductor device of claim 13 , wherein the logic semiconductor chip is arranged on the opposite main surface of the premolded leadframe.

15 . The semiconductor device of claim 13 , wherein the logic semiconductor chip is encapsulated in the semiconductor package.

16 . The semiconductor device of claim 1 , further comprising:

at least one passive electronic component arranged on the opposite main surface of the premolded leadframe.

17 . The semiconductor device of claim 16 , wherein the at least one passive electronic component comprises an inductor.

18 . The semiconductor device of claim 2 , further comprising:

a filling material at least partly filling the cavity and/or the gap.

19 . The semiconductor device of claim 1 , wherein the least one electrical contact is formed from a thicker portion of the electrically conductive plate that protrudes away from the thinner part of the electrically conductive plate.

20 . A semiconductor device, comprising:

a premolded leadframe, comprising a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface;

a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe, wherein the semiconductor package comprises a semiconductor chip and at least one electrical contact;

at least one passive electronic component arranged on the opposite main surface of the premolded leadframe; and

a stand-off configured to form a gap between the opposite main surface of the premolded leadframe and the inductor,

wherein surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush, and

wherein the at least one passive electronic component comprises an inductor.

21 . The semiconductor device of claim 20 , wherein the logic semiconductor chip is arranged in the gap.

22 . The semiconductor device of claim 20 , wherein the at least one passive electronic component comprises at least one capacitor.

23 . The semiconductor device of claim 20 , wherein the at least one capacitor is arranged in the gap.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (14)