Gate driving circuit and driving method thereof and display panel

1. A gate driving circuit comprising multiple stages of shift registers, the multiple stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals;

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals;

wherein K and N are both integers greater than 1, and K<N;

wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers;

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers;

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1; and

wherein K=6, i=3, and j=4.

2. The gate driving circuit of claim 1 , wherein reset signal terminals of (N−j+1)-th to N-th stages of first shift registers in the N stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers in the N stages of second shift registers are configured to receive a total reset signal.

3. The gate driving circuit of claim 1 , wherein the first shift registers are odd-numbered stages of shift registers in the multiple stages of shift registers, and the second shift registers are even-numbered stages of shift registers in the multiple stages of shift registers.

4. The gate driving circuit of claim 1 ,

wherein the N first shift registers are divided into at least one group of K cascaded first shift registers, and clock signal terminals of the K cascaded first shift registers are configured to receive the K first clock signals respectively; and

wherein the N second shift registers are divided into at least one group of K cascaded second shift registers, and clock signal terminals of the K cascaded second shift registers are configured to receive the K second clock signals respectively.

5. The gate driving circuit of claim 1 ,

wherein each of the first shift registers is configured to output a first output signal at an output signal terminal of said each of the first shift registers based on a signal of an input signal terminal of said each of the first shift registers under control of a first clock signal received by a clock signal terminal of said each of the first shift registers, and reset a pull-up node of said each of the first shift registers under control of a signal of a reset signal terminal of said each of the first shift registers; and

wherein each of the second shift registers is configured to output a second output signal at an output signal terminal of said each of the second shift registers based on a signal of an input signal terminal of said each of the second shift registers under control of a second clock signal received by a clock signal terminal of said each of the second shift registers, and reset a pull-up node of said each of the second shift registers under control of a signal of a reset signal terminal of said each of the first shift registers.

6. The gate driving circuit of claim 1 ,

wherein each of the first shift registers is further configured to reset a pull-up node of said each of the first shift registers under control of a signal of a total reset terminal of said each of the first shift registers; and

wherein each of the second shift registers is further configured to reset a pull-up node of said each of the second shift registers under control of a signal of a total reset terminal of said each of the second shift registers,

wherein total reset terminals of the N first shift registers and total reset terminals of the N second shift registers are configured to receive a total reset signal.

7. The gate driving circuit of claim 1 , wherein at least one shift register of the multiple stages of shift registers comprises:

an input circuit configured to input a signal of an input signal terminal of the shift register to a pull-up node of the shift register;

an output circuit coupled to the pull-up node, a clock signal terminal of the shift register and an output signal terminal of the shift register, and configured to provide a clock signal of the clock signal terminal to the output signal terminal under control of a potential of the pull-up node;

a control circuit coupled to a pull-down node of the shift register and the pull-up node, and configured to control a potential of the pull-down node according to the potential of the pull-up node; and

an reset circuit coupled to a reset signal terminal of the shift register and the pull-up node, and configured to reset the pull-up node under control of a signal of the reset signal terminal.

8. The gate driving circuit of claim 6 , wherein the pull-down node comprises a first pull-down node and a second pull-down node, and the control circuit comprises:

a first sub-circuit coupled to the first pull-down node and the pull-up node, and configured to control a potential of the first pull-down node according to a potential of the pull-up node; and

a second sub-circuit coupled to the second pull-down node and the pull-up node, and configured to control a potential of the second pull-down node according to the potential of the pull-up node.

9. The gate driving circuit of claim 8 , wherein the first sub-circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein:

a gate electrode of the first transistor and a first electrode of the first transistor are coupled to a first power signal terminal of the shift register, and a second electrode of the first transistor is coupled to a gate electrode of the second transistor;

a first electrode of the second transistor is coupled to the first electrode of the first transistor, and a second electrode of the second transistor is coupled to the first pull-down node;

a gate electrode of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to a reference signal terminal of the shift register, and a second electrode of the third transistor is coupled to the first pull-down node; and

a gate electrode of the fourth transistor is coupled to the pull-up node, a first electrode of the fourth transistor is coupled to the reference signal terminal, and a second electrode of the fourth transistor is coupled to the gate electrode of the second transistor.

10. The gate driving circuit of claim 9 , wherein the second sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein:

a gate electrode of the fifth transistor and a first electrode of the fifth transistor are coupled to a second power signal terminal of the shift register, and a second electrode of the fifth transistor is coupled to a gate electrode of the sixth transistor;

a first electrode of the sixth transistor is coupled to the first electrode of the fifth transistor, and a second electrode of the sixth transistor is coupled to the second pull-down node;

a gate electrode of the seventh transistor is coupled to the pull-up node, a first electrode of the seventh transistor is coupled to the reference signal terminal, and a second electrode of the seventh transistor is coupled to the second pull-down node; and

a gate electrode of the eighth transistor is coupled to the pull-up node, a first electrode of the eighth transistor is coupled to the reference signal terminal, and a second electrode of the eighth transistor is coupled to the gate electrode of the sixth transistor.

11. A gate driving circuit comprising multiple stages of shift registers, the multiple stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals;

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals;

wherein K and N are both integers greater than 1, and K≤N;

wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers;

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers;

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1; and

wherein K=8, i=4, and j=5.

12. A display panel comprising a gate driving circuit, wherein the gate driving circuit comprising multiple stages of shift registers, the multiple stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals;

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals;

wherein K and N are both integers greater than 1, and K≤N;

wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers;

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers;

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1; and

wherein K=6, i=3, and j=4.

13. The display panel of claim 12 , wherein reset signal terminals of (N−j+1)-th to N-th stages of first shift registers in the N stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers in the N stages of second shift registers are configured to receive a total reset signal.

14. A method of driving a gate driving circuit, wherein the gate driving circuit comprising multiple stages of shift registers, the multiple stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals;

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals;

wherein K and N are both integers greater than 1, and K≤N;

wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers;

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers;

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1; and

wherein K=6, i=3, and j=4;

wherein the method comprising:

in a first mode, turning on the multiple stages of shift registers, so that the N first shift registers of the multiple stages of shift registers generate the N first output signals under control of the K first clock signals and the N second shift registers of the multiple stages of shift registers generate the N second output signals under control of the K second clock signals; and

in a second mode, turning on the N first shift registers so that the N first shift registers generate the N first output signals under control of the K first clock signals, wherein the N first output signals are shifted sequentially, or turning on the N second shift registers in the second mode so that the N second shift registers generate the N second output signals under control of the K second clock signals, wherein the N second output signals are shifted sequentially.

15. The method of claim 14 , wherein reset signal terminals of (N−j+1)-th to N-th stages of first shift registers in the N stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers in the N stages of second shift registers are configured to receive a total reset signal.

16. The method of claim 14 , wherein, in the second mode,

the turning on the N first shift registers comprises: applying a valid first turn-on signal to the first to i-th stages of first shift registers in the N first shift registers, and applying an invalid second turn-on signal to the first to i-th stages of second shift registers in the N second shift registers; and

the turning on the N second shift registers comprises: applying a valid second turn-on signal to the first to i-th stages of second shift registers in the N second shift registers, and applying an invalid first turn-on signal to the first to i-th stages of first shift registers in the N first shift registers,

wherein i is an integer and 1≤i≤K/2.