The present application discloses a memory chip. The memory chip includes a nonvolatile status register and a control circuit. The nonvolatile status register includes a plurality of groups of registers, each group of the registers includes a flag register and at least one data register, the control circuit is connected to the nonvolatile status register, and is configured to control writing times of the nonvolatile status register being greater than erasing times of the nonvolatile status register.
1 . A memory chip, comprising:
a nonvolatile status register, wherein the nonvolatile status register comprises a plurality of groups of registers, each group of the registers comprises a flag register and at least one data register; and
a control circuit, wherein the control circuit is connected to the nonvolatile status register, and is configured to control the number of writing operations of the nonvolatile status register to be greater than the number of erasing operations of the nonvolatile status register.
2 . The memory chip according to claim 1 , wherein the control circuit is connected to the plurality of groups of the registers, and is configured to control the plurality of groups of the registers to perform the erasing operation once after performing the writing operations multiple times.
3 . The memory chip according to claim 2 , wherein the number of the writing operations performed between two continued erasing operations is equal to the number of groups of the registers in the nonvolatile status register.
4 . The memory chip according to claim 1 , wherein the flag register in one group of the registers is configured to indicate a storage state of the at least one data register in the same group of the registers, and the storage state comprises one of a writable state and a written state.
5 . The memory chip according to claim 4 , wherein the storage state is the writable state if a flag data of the flag register is 0xFF or 1; and the storage state is the written state if the flag data of the flag register is 0x00 or 0.
6 . The memory chip according to claim 1 , wherein after each group of the registers has performed one writing operation respectively, one erasing operation is performed on the plurality of groups of registers.
7 . The memory chip according to claim 1 , wherein the numbers of the at least one data register in respective groups of the registers are equal.
8 . The memory chip according to claim 1 , wherein the plurality of groups of the registers are arranged in a memory array according to an address sequence.
9 . The memory chip according to claim 1 , wherein each of the writing operations represents a writing operation performed on at least one group of the registers; each of the erasing operations represents an erasing operation performed on the whole nonvolatile status register, and the erasing operation is a step of erasing all data stored in a memory area where the nonvolatile status register is located.
10 . A memory chip, wherein the memory chip comprises a plurality of groups of registers, each group of the registers comprises a flag register and at least one data register, and the numbers of the at least one data registers in respective groups of the registers are equal; and
wherein at least two groups of the plurality of groups of registers are configured to respectively perform writing operations before one erasing operation is performed on the plurality of groups of registers once.
11 . The memory chip according to claim 10 , wherein after each group of the registers has performed one of the writing operations respectively, the erasing operation is performed on the plurality of groups of the registers once.
12 . The memory chip according to claim 10 , wherein the flag register in one group of the registers is configured to indicate a storage state of the same group of the registers, and the storage state comprises one of a writable state and a written state.
13 . The memory chip according to claim 12 , wherein the plurality of groups of the registers comprise a first group of the registers to a last group of the registers arranged according to an address sequence; the memory chip is configured to perform the following steps: reading the storage state of each group of the registers one by one according to the address sequence; judging whether the storage state of a current group of the registers that is currently read is the writable state; judging whether the current group of the registers is the first group of the registers if the storage state of the current group of the registers is the writable state; and directly writing data to be written to the current group of the registers if the current group of the registers is the first group of the registers.
14 . The memory chip according to claim 13 , wherein the memory chip is further configured to perform the following steps: recording stored data of each data register in a previous group, relative to the current group, of the registers to a buffer if the current group of the registers is not the first group of the registers; and writing the data to be written to the current group of the registers; wherein the data to be written comprises flag data, an un-updated part of the stored data stored in the buffer, and data to be updated, the flag data is written to the flag register in the current group of the registers, the un-updated part of the stored data stored in the buffer is written to data bits that correspond to the un-updated part and do not need to be updated in the current group of the registers, and the data to be updated is written to data bits that correspond to the data to be updated and need to be updated in the current group of the registers.
15 . The memory chip according to claim 13 , wherein the memory chip is further configured to perform the following steps: judging whether the current group of the registers is the last group of the registers if the storage state of the current group of the registers is not the writable state; and scanning the storage state of a next group of the registers if the current group of the registers is not the last group of the registers, and switching to the step of “judging whether the storage state of the current group of the registers is the writable state” as aforesaid.
16 . The memory chip according to claim 15 , wherein the memory chip is further configured to perform the following steps: performing the erasing operation on the plurality of groups of the registers after recording stored data of each of the data registers in the last group of the registers to a buffer, if the current group of the registers is the last group of the registers.
17 . The memory chip according to claim 16 , wherein the memory chip is further configured to perform the following steps: writing the data to be written to the first group of the registers; wherein the data to be written comprises flag data, an un-updated part of the stored data stored in a buffer, and data to be updated, the flag data is written to the flag register in the first group of the registers, the un-updated part of the stored data stored in the buffer is written to data bits that correspond to the un-updated part and do not need to be updated in the first group of the registers, and the data to be updated is written to data bits that correspond to the data to be updated and need to be updated in the first group of the registers.
18 . The memory chip according to claim 14 , wherein the flag data to be written in the current group of the registers is configured to indicate the storage state as the written state.
19 . The memory chip according to claim 10 , wherein the plurality of groups of registers comprise N groups of the registers, and the at least one data register comprises M data register, wherein the N is an integer greater than or equal to 2, and the M is an integer greater than or equal to 1.