Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices

1. A method for manufacturing a vertical junction field-effect transistor (JFET) device, the method comprising:

providing a III-nitride substrate having a first conductivity type,

forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;

forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth;

epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;

forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; and

epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.

2. The method of claim 1 wherein forming a plurality of trenches within the first III-nitride layer, comprises:

forming a first hardmask layer having a first set of openings on the first III-nitride layer to expose a first surface portion of the first III-nitride layer; and

etching the first surface portion of the first III-nitride layer using the first hardmask layer as a mask to form the plurality of trenches.

3. The method of claim 2 wherein epitaxially regrowing the second III-nitride structure in the trenches comprises:

selectively regrowing the second III-nitride structure in the trenches using a metalorganic chemical vapor deposition (MOCVD) process.

4. The method of claim 3 wherein the first hardmask layer is removed by wet etching prior to epitaxially regrowing the second III-nitride structure in the trenches.

5. The method of claim 1 wherein forming the plurality of III-nitride fins, each coupled to the first III-nitride layer, comprises:

forming a third III-nitride layer coupled to the first III-nitride layer, wherein the third III-nitride layer is characterized by a second dopant concentration greater than the first dopant concentration;

forming a second hardmask layer having a second set of openings on the third III-nitride layer to expose a second surface portion of the third III-nitride layer, wherein the second surface portion of the third III-nitride layer is aligned with each of the plurality of trenches; and

etching through the third III-nitride layer using the second hardmask layer as a mask to form the plurality of recess regions exposing the second III-nitride structure.

6. The method of claim 1 further comprising:

forming a source metal layer coupled to an upper surface of the plurality of III-nitride fins; and

forming a gate metal layer coupled to an upper surface of the III-nitride gate layer.

7. The method of claim 1 wherein forming the plurality of trenches comprises etching the plurality of trenches into the first III-nitride layer using a reactive ion etch (RIE) process.

8. The method of claim 7 wherein forming the plurality of trenches further comprises wet etching the plurality of trenches using tri-methyl ammonium hydroxide (TMAH).

9. The method of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.

10. A method for fabricating a metal-oxide field-effect transistor (MOSFET) device, the method comprising:

providing a III-nitride substrate having a first conductivity type;

forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by the first conductivity type and a first dopant concentration;

forming a plurality of first trenches within the first III-nitride layer, wherein the plurality of first trenches extend to a predetermined depth, and the plurality of first trenches are separated by a first portion of the first III-nitride layer;

epitaxially regrowing a second III-nitride structure in the first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;

epitaxially regrowing a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;

epitaxially regrowing a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type and a second dopant concentration;

forming a plurality of second trenches through the third and fourth III-nitride layers, wherein each of the plurality of second trenches is separated by a source region of the third and fourth III-nitride layers aligned with each the plurality of the first trenches;

forming a gate dielectric layer coupled to the fourth III-nitride layer and coupled to a sidewall and a bottom wall of the plurality of second trenches;

forming a gate metal layer coupled to the gate dielectric layer within the second trenches;

etching the gate dielectric layer on at least part of the source region of the third and fourth III-nitride layers aligned with each of the plurality of the first trenches to expose an upper surface portion of the fourth III-nitride layer; and

forming a source metal layer coupled to the upper surface portion of the fourth III-nitride layer.

11. The method of claim 10 wherein forming the plurality of second trenches through the third and fourth III-nitride layers comprises:

forming a second hardmask layer having a second set of openings on the fourth III-nitride layer to expose a second surface portion of the fourth III-nitride layer, wherein the second surface portion of the fourth III-nitride layer is aligned with at least part of the first portion of the first III-nitride layer; and

etching through the third and fourth III-nitride layers using the second hardmask layer as a mask to form the plurality of second trenches.

12. The method of claim 11 wherein etching through the third and fourth III-nitride layers comprises etching at least a portion of the first III-nitride layer.

13. The method of claim 11 wherein forming a plurality of second trenches through the third and fourth III-nitride layers comprises etching the plurality of second trenches through the third and fourth III-nitride layers using a reactive ion etch (RIE) process.

14. The method of claim 11 wherein forming a plurality of second trenches through the third and fourth III-nitride layers comprises wet etching the plurality of second trenches using tri-methyl ammonium hydroxide (TMAH).

15. The method of claim 11 wherein forming the plurality of second trenches through the third and fourth III-nitride layers comprises wet etching the second hardmask layer.