Performance of bank refresh
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
1. A memory controller, comprising:
an arbiter implemented as a circuit configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
2. The memory controller of claim 1 , further comprising:
a command queue for storing said memory access requests; and
a refresh control circuit operative to periodically generate same-bank refresh requests including the same-bank refresh request,
wherein the arbiter is further operable to select commands from the command queue and to send the commands to a memory interface.
3. The memory controller of claim 2 , wherein:
the refresh control circuit is operative to generate a same-bank refresh ready signal in response to detecting a predetermined number of row-hit commands in the command queue; and
the arbiter is responsive to the same-bank refresh ready signal to send a corresponding same-bank refresh command to the memory interface.
4. The memory controller of claim 3 , wherein the refresh control circuit is further operative to generate the same-bank refresh ready signal in response to the same-bank refresh request achieving an urgent status.
5. The memory controller of claim 3 , wherein the arbiter is further operative to delay sending the corresponding same-bank refresh command until at least a first predetermined amount of time has passed after a last activate command.
6. The memory controller of claim 3 , wherein the arbiter stops elevating the priority of the memory access requests that generate the row activate commands in the command queue in response to sending the corresponding same-bank refresh command.
7. The memory controller of claim 2 , wherein the arbiter selectively elevates page misses to different banks in the same rank as banks to be refreshed.
8. A data processing system comprising:
a data processor for generating memory access requests; and
an arbiter implemented as a circuit configured to elevate a priority of the memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
9. The data processing system of claim 8 , further comprising:
a command queue for storing said memory access requests; and
a refresh control circuit operative to periodically generate same-bank refresh requests including the same-bank refresh request,
wherein the arbiter is further operable to select commands from the command queue and to send the commands to a memory interface.
10. The data processing system of claim 9 , wherein:
the refresh control circuit is operative to generate a same-bank refresh ready signal in response to detecting a predetermined number of row-hit commands in the command queue; and
the arbiter is responsive to the same-bank refresh ready signal to send a corresponding same-bank refresh command to the memory interface.
11. The data processing system of claim 10 , wherein the refresh control circuit is further operative to generate the same-bank refresh ready signal in response to the same-bank refresh request achieving an urgent status.
12. The data processing system of claim 10 , wherein the arbiter is further operative to delay sending the same-bank refresh command until at least a first predetermined amount of time has passed after a last activate command.
13. The data processing system of claim 10 , wherein the arbiter stops elevating the priority of the memory access requests that generate the row activate commands in the command queue in response to sending the same-bank refresh command.
14. The data processing system of claim 13 , wherein the arbiter stops sending the memory access requests that generate the row activate commands for a second predetermined amount of time after sending the corresponding same-bank refresh command to the memory interface.
15. The data processing system of claim 14 , wherein the arbiter stops sending memory access commands to the same bank as the same-bank refresh command for a third predetermined amount of time after sending the corresponding same-bank refresh command to the memory interface, wherein the third predetermined amount of time is longer than the second predetermined amount of time.
16. The data processing system of claim 9 , wherein the arbiter selectively elevates page misses to different banks in the same rank as banks to be refreshed.
17. A method, comprising:
storing memory access requests in a command queue;
periodically generating same-bank refresh requests;
selecting commands from the command queue and sending a same-bank refresh command to a memory interface in response to a same-bank refresh request; and
elevating a priority of the memory access requests in the command queue that generate row activate commands in response to receiving the same-bank refresh request.
18. The method of claim 17 , further comprising:
generating a same-bank refresh ready signal in response to one of detecting a predetermined number of row-hit commands in the command queue and the same-bank refresh request achieving an urgent status; and
sending a corresponding same-bank refresh command to the memory interface responsive to the same-bank refresh ready signal.
19. The method of claim 18 , further comprising:
stopping elevating the priority of the memory access requests that generate the row activate commands in the command queue in response to sending the corresponding same-bank refresh command.
20. The method of claim 17 , wherein elevating comprises:
selectively elevating page misses to different banks in the same rank as banks to be refreshed.