IP Library Granted Patent US 11,972,984
Granted Patent B2
US 11,972,984 · App. 18/088,631 · Granted Apr 30, 2024

Semiconductor device and method for fabricating the same

Inventors: Ching-Ling Lin (Kaohsiung, TW); Wen-An Liang (Tainan, TW); Chen-Ming Huang (Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/823481H01L21/764H01L21/823431H01L27/0886H01L29/0649H01L29/66545H01L29/66795H01L29/785
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,972,984
App. No.
18/088,631
Granted
Apr 30, 2024
Kind
B2
Abstract

A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Claims (19)

1. A semiconductor device, comprising:

a fin-shaped structure on a substrate;

a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure;

a first spacer around and not directly under the gate structure;

a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure, wherein the SDB structure comprises:

a bottom portion; and

a top portion on the bottom portion, wherein the top portion and the bottom portion comprise different widths and a top surface of the bottom portion is higher than a top surface of the fin-shaped structure; and

a second spacer around the SDB structure, wherein the first spacer and the second spacer comprise same widths and different heights.

2. The semiconductor device of claim 1 , further comprising:

a contact etch stop layer (CESL) between the first spacer and the second spacer.

3. The semiconductor device of claim 2 , wherein the CESL is U-shaped.

4. The semiconductor device of claim 2 , wherein a top surface of the CESL adjacent to the second spacer is lower than a top surface of the CESL adjacent to the first spacer.

5. The semiconductor device of claim 1 , wherein a top surface of the bottom portion is even with a top surface of the gate structure.

6. The semiconductor device of claim 1 , wherein the SDB structure comprises:

a liner; and

a dielectric layer on the liner, wherein the liner and the dielectric layer comprise different material.

7. The semiconductor device of claim 1 , further comprising an air gap in the SDB structure.

8. The semiconductor device of claim 1 , wherein the fin-shaped structure is disposed extending along a first direction and the SDB structure is disposed extending along a second direction.

9. The semiconductor device of claim 8 , wherein the first direction is orthogonal to the second direction.

Priority Claims (1)
CN 201711262580.1 · Dec 4, 2017 · national
Continuity (3)
Continuation 16859959 · Apr 27, 2020
Division 15859775 · Jan 2, 2018
Related Publication 20230135742A1 · May 4, 2023