Memory device and operating method thereof
A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSG unsel ), and suspending programming or verifying of the memory cell in a suspend phase.
1. A method of programming a memory device, the memory device comprising a plurality of memory strings, each memory string comprising a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and a plurality of memory cells between the top transistor and the bottom transistor, each memory cell connected to a word line (WL), the method comprising:
applying a plurality of program pulses to a memory cell of the memory device in a program phase;
verifying a voltage value of the memory cell in a verify phase;
receiving a suspend command and performing a suspend operation in response to the suspend command;
applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein applying the discharge pulse comprises applying:
a first voltage pulse to an unselected top select gate (TSG unsel ), the first voltage pulse weighted to a first turn-on voltage V ON1 of the TSG unsel ;
a second voltage pulse to a selected top select gate (TSG sel ), the second voltage pulse weighted to a second turn-on voltage V tsg of the TSG sel ;
a third voltage pulse to a bottom select gate (BSG), the third voltage pulse weighted to a third turn-on voltage V ON2 of the BSG;
a fourth voltage pulse to an unselected word line (WL unsel ), the fourth voltage pulse weighted to a first pass voltage V PASS1 of the WL unsel ; and
a fifth voltage pulse to a selected word line (WL sel ), the fifth voltage pulse weighted to a second pass voltage V PASS2 of the WL unsel ; and
suspending programming or verifying of the memory cell in a suspend phase.
2. The method of claim 1 , wherein the suspend command is received during the program phase.
3. The method of claim 2 , wherein the discharge pulse is applied between an end of a program phase loop of the program phase and a start of the suspend phase.
4. The method of claim 3 , wherein applying the discharge pulse comprises applying a merged discharge pulse, wherein the merged discharge pulse overlaps the end of the program phase loop and a start of the discharge phase.
5. The method of claim 1 , wherein:
the first turn-on voltage V ON1 can be about 0.5 V to about 5 V;
the second turn-on voltage V tsg can be about 0.5 V to about 5 V;
the third turn-on voltage V ON2 can be about 0.5 V to about 5 V;
the first pass voltage V PASS1 can be about 0.5 V to about 5 V; and
the second pass voltage V PASS2 can be about 0.5 V to about 5 V.
6. The method of claim 1 , wherein the suspend command is received during the verify phase.
7. The method of claim 6 , wherein performing the suspend operation comprises immediately stopping the verify phase at a first verify state thereby decreasing a time interval of the suspend phase.
8. The method of claim 7 , further comprising resuming the verify phase at a second verify state after the first verify state.
9. The method of claim 6 , wherein performing the suspend operation comprises completing the entire verify phase before the discharge phase.
10. The method of claim 6 , wherein applying the discharge pulse comprises applying a merged discharge pulse, wherein the merged discharge pulse overlaps an end of a verify phase loop of the verify phase and a start of the discharge phase.
11. The method of claim 10 , wherein the suspend command is received at the end of the verify phase loop, at a start of a sixth voltage pulse to a programmed bit line (BL pgm ), and during the first voltage pulse of the TSG unsel .
12. A memory device comprising:
a memory array comprising a plurality of memory strings, each memory string comprising a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and a plurality of memory cells between the top transistor and the bottom transistor, each memory cell connected to a word line (WL); and
a peripheral circuit coupled to the memory array, the peripheral circuit configured to:
apply a plurality of program pulses to a memory cell of the memory array in a program phase;
verify a voltage value of the memory cell in a verify phase;
receive a suspend command and perform a suspend operation in response to the suspend command;
apply a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein applying the discharge pulse comprises applying:
a first voltage pulse to an unselected top select gate (TSG unsel ), the first voltage pulse weighted to a first turn-on voltage V ON1 of the TSG unsel ;
a second voltage pulse to a selected top select gate (TSG sel ), the second voltage pulse weighted to a second turn-on voltage V tsg of the TSG sel ;
a third voltage pulse to a bottom select gate (BSG), the third voltage pulse weighted to a third turn-on voltage V ON2 of the BSG;
a fourth voltage pulse to an unselected word line (WL unsel ), the fourth voltage pulse weighted to a first pass voltage V PASS1 of the WL unsel ; and
a fifth voltage pulse to a selected word line (WL sel ), the fifth voltage pulse weighted to a second pass voltage V PASS2 of the WL unsel ; and
suspend programming or verifying of the memory cell in a suspend phase.
13. The memory device of claim 12 , wherein:
the peripheral circuit receives the suspend command during the program phase, and
the peripheral circuit is further configured to apply a merged discharge pulse, the merged discharge pulse overlapping an end of a program phase loop of the program phase and a start of the discharge phase.
14. The memory device of claim 12 , wherein the peripheral circuit receives the suspend command during the verify phase.
15. The memory device of claim 14 , wherein the suspend operation comprises immediately stopping the verify phase at a first verify state after receiving the suspend command thereby decreasing a time interval of the suspend phase.
16. The memory device of claim 14 , wherein the suspend operation comprises completing the entire verify phase before the discharge phase after receiving the suspend command.
17. A memory system comprising:
a memory device comprising a plurality of memory strings, each memory string comprising a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and a plurality of memory cells between the top transistor and the bottom transistor, each memory cell connected to a word line (WL); and
a memory controller coupled to the memory device, the memory controller configured to:
apply a plurality of program pulses to a memory cell of the memory device in a program phase;
verify a voltage value of the memory cell in a verify phase;
receive a suspend command and perform a suspend operation in response to the suspend command;
apply a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein applying the discharge pulse comprises applying:
a first voltage pulse to an unselected top select gate (TSG unsel ), the first voltage pulse weighted to a first turn-on voltage V ON1 of the TSG unsel ,
a second voltage pulse to a selected top select gate (TSG sel ), the second voltage pulse weighted to a second turn-on voltage V tsg of the TSG sel ;
a third voltage pulse to a bottom select gate (BSG), the third voltage pulse weighted to a third turn-on voltage V ON2 of the BSG;
a fourth voltage pulse to an unselected word line (WL unsel ), the fourth voltage pulse weighted to a first pass voltage V PASS1 of the WL unsel , and
a fifth voltage pulse to a selected word line (WL sel ), the fifth voltage pulse weighted to a second pass voltage V PASS2 of the WL unsel ; and
suspend programming or verifying of the memory cell in a suspend phase.
18. The memory system of claim 17 , wherein:
the memory controller receives the suspend command during the program phase, and the memory controller is further configured to apply a merged discharge pulse, the merged discharge pulse overlapping an end of a program phase loop of the program phase and a start of the discharge phase.