Granted Patent B2

US 12,408,421 · App. 18/090,721 · Granted Sep 2, 2025

Inventor: Tse-Yao Huang (Taipei, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H10D84/83H10D64/513H10D64/518H10D64/667H10D84/014H10D84/0142H10D84/038

Abstract

Claims (47)

1. A semiconductor device, comprising:

a substrate;

a peripheral gate structure comprising:

a peripheral gate insulating layer inwardly positioned in the substrate and comprising a U-shaped cross-sectional profile;

a peripheral work function layer positioned on the peripheral gate insulating layer and comprising a recess;

a first peripheral interconnect layer positioned on the peripheral work function layer;

a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer; and

a peripheral capping layer positioned on the first peripheral interconnect layer, wherein the peripheral work function layer comprises titanium, titanium nitride, silicon, silicon germanium, or a combination thereof, wherein the first peripheral liner layer comprises graphene, wherein the first peripheral interconnect layer comprises tungsten, tungsten nitride, or a combination thereof, wherein the first peripheral interconnect layer comprises a bottom portion positioned in the recess and a top portion positioned on the bottom portion, wherein a width of the bottom portion is less than a width of the top portion;

a second peripheral interconnector layer positioned between the first peripheral interconnect layer and the peripheral capping layer; and

a second peripheral liner layer positioned between the first peripheral interconnect layer and the second peripheral interconnector layer;

wherein the second peripheral liner layer comprises graphene;

wherein the second peripheral interconnector layer comprises molybdenum;

wherein the peripheral gate insulating layer comprises silicon oxide, silicon nitride, a high-k material, or a combination thereof;

wherein a top surface of the second peripheral interconnector layer and a top surface of the first peripheral liner layer are substantially coplanar.

2. A semiconductor device, comprising:

a substrate comprising an array area and a peripheral area;

an array gate structure positioned in the array area of the substrate;

a peripheral gate structure comprising:

a peripheral gate insulating layer inwardly positioned in the peripheral area of the substrate and comprising a U-shaped cross-sectional profile;

a peripheral work function layer positioned on the peripheral gate insulating layer and comprising a recess;

a first peripheral interconnect layer positioned on the peripheral work function layer;

a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer; and

a peripheral capping layer positioned on the first peripheral interconnect layer;

a second peripheral interconnector layer; and

a second peripheral liner layer;

wherein a width of the peripheral gate structure is greater than two times a width of the array gate structure;

wherein the peripheral work function layer comprises titanium, titanium nitride, silicon, silicon germanium, or a combination thereof;

wherein the first peripheral liner layer comprises graphene; and

wherein the first peripheral interconnect layer comprises tungsten, tungsten nitride, or a combination thereof;

wherein the first peripheral interconnect layer comprises a bottom portion positioned in the recess and a top portion positioned on the bottom portion, wherein a width of the bottom portion is less than a width of the top portion;

wherein the second peripheral interconnector layer is positioned between the first peripheral interconnect layer and the peripheral capping layer, wherein the second peripheral liner layer is positioned between the first peripheral interconnect layer and the second peripheral interconnector layer;

wherein the second peripheral liner layer comprises graphene;

wherein the second peripheral interconnector layer comprises molybdenum; and

wherein the peripheral gate insulating layer comprises silicon oxide, silicon nitride, a high-k material, or a combination thereof;

wherein a top surface of the second peripheral interconnector layer and a top surface of the first peripheral liner layer are substantially coplanar.

3. The semiconductor device of claim 2 , wherein the array gate structure comprises:

an array gate insulating layer inwardly positioned in the array area of the substrate and comprising a U-shaped cross-sectional profile;

an array work function layer positioned on the array gate insulating layer;

a first array interconnector layer positioned on the array work function layer;

a first array liner layer positioned between the array work function layer and the first array interconnector layer;

a second array interconnector layer positioned on the first array interconnector layer;

a second array liner layer positioned between the second array interconnector layer and the first array interconnector layer; and

an array capping layer positioned on the second array interconnector layer.

4. The semiconductor device of claim 3 , wherein a top surface of the array work function layer and a top surface of the peripheral work function layer are substantially coplanar.

5. The semiconductor device of claim 3 , wherein a top surface of the array work function layer and a top surface of the peripheral work function layer are at different vertical levels.

6. The semiconductor device of claim 3 , wherein a top surface of the first array interconnector layer and a top surface of the first peripheral interconnect layer are substantially coplanar.

7. The semiconductor device of claim 3 , wherein a top surface of the first array interconnector layer and a top surface of the first peripheral interconnect layer are at different vertical levels.

Assignments (1)

Continuity (1)

References Cited (14)