Clock signal generation circuit, DC/DC converter, PWM signal generator, and vehicle

1. A clock signal generation circuit comprising:

a triangular wave generation circuit configured to generate a triangular wave signal:

a pseudo-random number generation circuit configured to generate a pseudo-random number signal;

a limiter circuit configured to perform a limitation process of limiting an amount of change per unit time in the pseudo-random number signal and generate the pseudo-random number signal subjected to the limitation process as a limiter signal;

a linear arithmetic circuit configured to generate a frequency control signal by performing a linear arithmetic operation on the triangular wave signal and the limiter signal; and

an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal.

2. The clock signal generation circuit of claim 1 , wherein the pseudo-random number generation circuit updates and outputs a value of the pseudo-random number signal based on the unit time as a period, and

wherein the limiter circuit generates a signal, which is based on an output of the pseudo-random number generation circuit and the amount of change per unit time is limited to a predetermined value or less, as the limiter signal.

3. The clock signal generation circuit of claim 1 , wherein in the linear arithmetic operation, the linear arithmetic circuit adds one of the triangular wave signal and the limiter signal to the other one, or subtracts one of the triangular wave signal and the limiter signal from the other one.

4. A clock signal generation circuit comprising:

a triangular wave generation circuit configured to generate a triangular wave signal:

a pseudo-random number generation circuit configured to generate a pseudo-random number signal:

a linear arithmetic circuit configured to generate a linear arithmetic result signal by performing a linear arithmetic operation on the triangular wave signal and the pseudo-random number signal:

a limiter circuit configured to perform a limitation process of limiting an amount of change per unit time in the linear arithmetic result signal and generate the linear arithmetic result signal subjected to the limitation process as a frequency control signal; and

an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal.

5. The clock signal generation circuit of claim 4 , wherein the pseudo-random number generation circuit updates and outputs a value of the pseudo-random number signal based on the unit time as a period,

wherein the linear arithmetic circuit updates and outputs a value of the linear arithmetic result signal based on the unit time as a period, and

wherein the limiter circuit generates a signal, which is based on an output of the linear arithmetic circuit and the amount of change per unit time is limited to a predetermined value or less, as the frequency control signal.

6. The clock signal generation circuit of claim 4 , wherein in the linear arithmetic operation, the linear arithmetic circuit adds one of the triangular wave signal and the pseudo-random number signal to the other one, or subtracts one of the triangular wave signal and the pseudo-random number signal from the other one.

7. A DC/DC converter comprising:

the signal generation circuit of claim 1 ; and

a power conversion circuit configured to generate a second DC voltage by switching a first DC voltage at a switching frequency corresponding to the clock signal.

8. A PWM signal generator comprising:

the signal generation circuit of claim 1 ; and

a pulse width modulation circuit configured to generate a pulse width modulation signal based on the clock signal.

9. An in-vehicle semiconductor device comprising the clock signal generation circuit of claim 1 .