IP Library › Granted Patent US 12,542,447
Granted Patent B2
US 12,542,447 · App. 18/091,911 · Granted Feb 3, 2026

Simultaneous charging and power export using n-leg converter

Inventors: Mohammad Nanda R. Marwali (Irvine, CA); Zahra Mohajerani (Los Angeles, CA); Muhammad Mobeen Mahmood (Irving, TX); Yuxiang Shi (Cary, NC); Yanjun Shi (Torrance, CA)
Assignee: Rivian IP Holdings, LLC
H02J7/0068B60L53/22H02J7/02H02M1/0058H02M7/219B60L2210/30H02J2207/20
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,542,447
App. No.
18/091,911
Granted
Feb 3, 2026
Kind
B2
Abstract

Systems and methods for simultaneously generating a charging signal and a power signal via a converter having a first leg, a second leg, a third leg, and a fourth leg are disclosed herein. An alternating current (AC) source input voltage having a fundamental frequency of a power system is received. The charging signal is generated by the first leg and the second leg and the power signal is generated by the second leg, the third leg, and the fourth leg. The second leg is switched at the fundamental frequency and the first leg, the third leg, and the fourth leg are switched at frequencies higher than the fundamental frequency.

Claims (24)

1 . A method for simultaneously generating an direct current (DC) charging signal and an AC power signal via a converter having a first leg, a second leg, a third leg, and a fourth leg, the method comprising: receiving an AC source input voltage having a fundamental frequency of a power system; generating, by the first leg and the second leg, the DC charging signal; and generating, by the second leg, the third leg, and the fourth leg, the AC power signal, wherein the second leg is switched at the fundamental frequency and the first leg, the third leg, the fourth leg are switched at frequencies higher than the fundamental frequency, and the DC charging signal and the AC power signal are generated for simultaneous output.

2 . The method of claim 1 , wherein the DC charging signal and the AC power signal are synchronized to the received AC source input voltage using a phase-lock-loop such that a polarity of a DC charging voltage is equal to a polarity of the power signal.

3 . The method of claim 1 , further comprising inserting a blanking period at zero crosses of the charging voltage and the AC power signal, wherein during each blanking period, switches of the first leg, the second leg, the third leg, and the fourth leg are switched off.

4 . The method of claim 1 , wherein the AC power signal is a split-phase power signal having a root mean square voltage of 240V.

5 . The method of claim 1 , wherein the fundamental frequency is within a range of 50-60 Hz.

6 . The method of claim 1 , wherein the switching frequencies of the first leg, the third leg, and the fourth leg are within a range of 1 kHz-10 MHz.

7 . A method for simultaneously generating a split-phase power signal and a direct current (DC) charging signal via a converter having a first leg, a second leg, a third leg, and a fourth leg, the method comprising: receiving an alternating current AC source input voltage having a fundamental frequency of a power system; switching, at a first frequency, the first leg comprising a first switch and a second switch to generate a first signal; switching, at the fundamental frequency, the second leg comprising a third switch and a fourth switch to generate a second signal; switching, at a third frequency, the third leg comprising a fifth switch and a sixth switch to generate a third signal; and switching, at a fourth frequency, the fourth leg comprising a seventh switch and an eight switch to generate a fourth signal; generating, based on the first signal and the second signal, a DC charging voltage for charging a battery connected to the converter; and generating, based on the second signal, the third signal, and the fourth signal, the split-phase power signal, wherein the DC charging voltage and the split-phase power signal are generated for simultaneous output.

8 . The method of claim 7 , wherein the split-phase power signal and the DC charging voltage are synchronized to the received AC source input voltage using a phase-lock-loop such that a polarity of the DC charging voltage is equal to a polarity of the split-phase power signal.

9 . The method of claim 7 , further comprising inserting a blanking period at zero crosses of the DC charging voltage and the split-phase power signal, wherein during each blanking period, each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eight switch are switched off.

10 . The method of claim 7 , wherein the fundamental frequency is within a range of 50-60 Hz.

11 . The method of claim 7 , wherein each of the first frequency, the third frequency, and the fourth frequency is within a range of 1 kHz-10 MHz.

12 . The method of claim 7 , wherein:

each of the third switch and the fourth switch comprises a metal-oxide-semiconductor field effect transistor (MOSFET), insulated-gate bipolar transistor, or any combination thereof; and

each of the first switch, the second switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch comprise a wide-band-gap semiconductor device.

13 . The method of claim 7 , wherein a root mean square voltage of the split-phase power signal is 240V.

14 . A method for simultaneously generating a split-phase power signal and a direct current (DC) charging signal via a converter having a first leg, a second leg, a third leg, and a fourth leg, the method comprising: receiving an alternating current AC source input voltage having a fundamental frequency of a power system; switching, at a first frequency, the first leg comprising a first switch and a second switch to generate a first signal; switching, at a second frequency, the second leg comprising a third switch and a fourth switch to generate a second signal; switching, at a third frequency, the third leg comprising a fifth switch and a sixth switch to generate a third signal; and switching, at the fundamental frequency, the fourth leg comprising a seventh switch and an eighth switch to generate a fourth signal; generating, based on the first signal, the second signal, and the fourth signal, an ADC charging voltage for charging a battery connected to the converter; and generating, based on the third signal and the fourth signal, the single-phase power signal, wherein the A DC charging voltage and the single-phase power signal are generated for simultaneous output.

15 . The method of claim 14 , wherein the single-phase power signal and the DC charging voltage are synchronized to the received AC source input voltage using a phase-lock-loop such that a polarity of the DC charging voltage is equal to a polarity of the single-phase power signal.

16 . The method of claim 14 , further comprising inserting a blanking period at zero crosses of the DC charging voltage and the single-phase power signal, wherein during each blanking period, each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eight switch are switched off.

17 . The method of claim 14 , wherein the fundamental frequency is within a range of 50-60 Hz.

18 . The method of claim 14 , wherein each of the first frequency, the second frequency, and the third frequency is within a range of 1 kHz-10 MHz.

19 . The method of claim 14 , wherein:

each of the seventh switch and the eighth switch comprises a metal-oxide-semiconductor field effect transistor (MOSFET), insulated-gate bipolar transistor, or any combination thereof; and

each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch comprise a wide-band-gap semiconductor device.

20 . The method of claim 14 , wherein a root mean square voltage of the single-phase power signal is 120V.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: MARWALI, MOHAMMAD NANDA R.; MOHAJERANI, ZAHRA; MAHMOOD, MUHAMMAD MOBEEN; SHI, YUXIANG; SHI, YANJUN
To: RIVIAN AUTOMOTIVE, LLC
Reel/Frame 062358/0654 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: RIVIAN AUTOMOTIVE, LLC
To: RIVIAN IP HOLDINGS, LLC
Reel/Frame 062358/0693 →
Continuity (1)
Related Publication 20240222990A1 · Jul 4, 2024
References Cited (29)
US 5656915A · Eaves · 1997 [cited by applicant]
US 9035608B2 · Loudot · 2015 [cited by examiner]
US 10013007B2 · Liu · 2018 [cited by examiner]
US 11177682B2 · Chang · 2021 [cited by examiner]
US 11251625B2 · Sun · 2022 [cited by examiner]
US 11413983B2 · Ge · 2022 [cited by examiner]
US 11757371B1 · Marwali · 2023 [cited by examiner]
US 11855543B2 · Teng · 2023 [cited by examiner]
US 11865933B2 · Teng · 2024 [cited by examiner]
US 11916474B2 · Everts · 2024 [cited by examiner]
US 20140097792A1 · Su · 2014 [cited by examiner]
US 20190299792A1 · Kim · 2019 [cited by examiner]
US 20200083727A1 · Sun · 2020 [cited by examiner]
US 20210221249A1 · Ge · 2021 [cited by examiner]
US 20220360184A1 · Teng · 2022 [cited by examiner]
US 20230231470A1 · Ammanamanchi · 2023 [cited by examiner]
US 20230353045A1 · Mino · 2023 [cited by examiner]
US 20240429831A1 · Sreedhar · 2024 [cited by examiner]
CN 108258906A · 2018 [cited by examiner]
CN 112389227A · 2021 [cited by applicant]
DE 102009000096A1 · 2010 [cited by applicant]
DE 102011075927A1 · 2012 [cited by applicant]
JP 2014161142A · 2014 [cited by examiner]
WO WO2007148531A1 · 2007 [cited by examiner]
WO WO2021205040A1 · 2021 [cited by examiner]
Improving light load power factor for GaN based Totem Pole bridgeless PFC using digital phase locked loop based vector cancellation & tracking error compensation. M Bhardwaj, SY Yu, Z Ye, S Choudhury 2018 IEEE Applied P… [cited by examiner]
Machine translation JP-2014161142-A (Year: 2014). [cited by examiner]
Machine translation WO-2007148531-A1 (Year: 2007). [cited by examiner]
Machine Translation CN_108258906_A (Year: 2018). [cited by examiner]