Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
1. A clock generating circuit comprising:
a buffer circuit configured to non-invert an input clock signal to generate an output clock signal;
a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change; and
a compensating circuit configured to invert the output clock signal according to the first and second control voltages to generate a feedback signal using a single inversion stage, and configured to provide the feedback signal to the input clock signal,
wherein the feedback signal is a single inversion of the output clock signal.
2. The clock generating circuit of claim 1 , wherein the voltage control circuit is configured to generate the first control voltage having the voltage level, which complementarily changes with reference to a voltage level of the power voltage, and configured to generate the second control voltage having the voltage level, which complementarily changes with reference to the first control voltage.
3. The clock generating circuit of claim 1 , wherein the voltage control circuit includes:
a bias generating circuit configured to generate a first bias voltage having a constant voltage level regardless of the voltage level change of the power voltage and configured to generate a second bias voltage having a varying voltage level according to the voltage level change of the power voltage; and
a control voltage generating circuit configured to generate the first control voltage and the second control voltage having the voltage levels varying in proportion to voltage level difference between the first bias voltage and the second bias voltage.
4. The clock generating circuit of claim 3 , wherein the control voltage generating circuit includes:
an amplifier including a positive input node receiving the second bias voltage and a negative input node receiving an output voltage, the amplifier configured to generate the output voltage;
an inverting amplifier including a positive input node receiving the first bias voltage and a negative input node receiving the output voltage, the inverting amplifier configured to generate the first control voltage; and
a voltage driver configured to generate the second control voltage having the voltage level, which complementarily changes with reference to a voltage level change of the first control voltage.
5. The clock generating circuit of claim 1 ,
wherein the compensating circuit is configured to change a voltage level of the input clock signal by a greater amount as the voltage level of the first control voltage is raised and the voltage level of the second control voltage is lowered, and
wherein the compensating circuit is configured to change the voltage level of the input clock signal by a lesser amount as the voltage level of the first control voltage is lowered and the voltage level of the second control voltage is raised.
6. The clock generating circuit of claim 1 ,
wherein the compensating circuit includes an inverter configured to invert the output clock signal to generate the feedback signal and configured to provide the feedback signal to the input clock signal,
wherein a driving force with which the inverter drives the feedback signal is adjusted on a basis of the first control voltage and the second control voltage.
7. The clock generating circuit of claim 1 , wherein the compensating circuit includes:
a plurality of inverters configured to invert the output control signal to generate the feedback signal, a driving force with which the plurality of inverters drives the feedback signal being adjusted on a basis of the first control voltage and the second control voltage; and
a compensation controller configured to determine, based on an enable signal and a turn-on signal, a number of inverters to be activated among the plurality of inverters.
8. A clock generating circuit comprising:
a first buffer circuit configured to non-invert a first input clock signal to generate a first output clock signal;
a second buffer circuit configured to non-invert a second input clock signal to generate a second output clock signal, the second input clock signal being a complementary clock signal of the first input clock signal;
a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
a first compensating circuit configured to invert the first output clock signal according to the first and second control voltages to generate a first feedback signal using a single inversion stage, and configured to provide the first feedback signal to the first input clock signal; and
a second compensating circuit configured to invert the second output clock signal according to the first and second control voltages to generate a second feedback signal, and configured to provide the second feedback signal to the second input clock signal,
wherein the first feedback signal is a single inversion of the first output clock signal.
9. The clock generating circuit of claim 8 , wherein the voltage control circuit is configured to generate the first control voltage having the voltage level, which complementarily changes with reference to a voltage level of the power voltage, and configured to generate the second control voltage having the voltage level, which complementarily changes with reference to the voltage level of the first control voltage.
10. The clock generating circuit of claim 8 , wherein the voltage control circuit includes:
a bias generating circuit configured to generate a first bias voltage having a constant voltage level regardless of the voltage level change of the power voltage and configured to generate a second bias voltage having a varying voltage level according to the voltage level change of the power voltage; and
a control voltage generating circuit configured to generate the first control voltage and the second control voltage having the voltage levels varying in proportion to voltage level difference between the first bias voltage and the second bias voltage.
11. The clock generating circuit of claim 10 , wherein the control voltage generating circuit includes:
an amplifier including a positive input node receiving the second bias voltage and a negative input node receiving an output voltage, the amplifier configured to generate the output voltage;
an inverting amplifier including a positive input node receiving the first bias voltage and a negative input node receiving the output voltage, the inverting amplifier configured to generate the first control voltage; and
a voltage driver configured to generate the second control voltage having the voltage level, which complementarily changes with reference to a voltage level change of the first control voltage.
12. The clock generating circuit of claim 8 ,
wherein the first compensating circuit includes at least one inverter configured to invert the first output clock signal to generate the first feedback signal and configured to provide the first feedback signal to the first input clock signal,
wherein a driving force with which the at least one inverter drives the first feedback signal is adjusted on a basis of the first control voltage and the second control voltage.
13. The clock generating circuit of claim 8 ,
wherein the second compensating circuit includes at least one inverter configured to invert the second output clock signal to generate the second feedback signal and configured to provide the second feedback signal to the second input clock signal,
wherein a driving force with which the at least one inverter drives the second feedback signal is adjusted on a basis of the first control voltage and the second control voltage.
14. A semiconductor apparatus including a clock distribution network,
wherein the clock distribution network includes:
a clock receiving circuit configured to receive an external clock signal and a complementary external clock signal to generate a first input clock signal and a second input clock signal;
a first buffer circuit configured to non-invert the first input clock signal to generate a first output clock signal;
a second buffer circuit configured to non-invert the second input clock signal to generate a second output clock signal;
a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change;
a first compensating circuit configured to invert the first output clock signal according to the first and second control voltages to generate a first feedback signal using a single inversion stage, and configured to provide the first feedback signal to the first input clock signal;
a second compensating circuit configured to invert the second output clock signal according to the first and second control voltages to generate a second feedback signal, and configured to provide the second feedback signal to the second input clock signal; and
a dividing circuit configured to divide the first output clock signal and the second output clock signal to generate a plurality of internal clock signals,
wherein the first feedback signal is a single inversion of the first output clock signal.
15. The semiconductor apparatus of claim 14 , wherein the voltage control circuit includes:
a bias generating circuit configured to generate a first bias voltage having a constant voltage level regardless of the voltage level change of the power voltage and configured to generate a second bias voltage having a varying voltage level according to the voltage level change of the power voltage; and
a control voltage generating circuit configured to generate the first control voltage and the second control voltage having the voltage levels varying in proportion to voltage level difference between the first bias voltage and the second bias voltage.
16. The semiconductor apparatus of claim 15 , wherein the control voltage generating circuit includes:
an amplifier including a positive input node receiving the second bias voltage and a negative input node receiving an output voltage, the amplifier configured to generate the output voltage;
an inverting amplifier including a positive input node receiving the first bias voltage and a negative input node receiving the output voltage, the inverting amplifier configured to generate the first control voltage; and
a voltage driver configured to generate the second control voltage having the voltage level, which complementarily changes with reference to a voltage level change of the first control voltage.
17. The semiconductor apparatus of claim 14 , further comprising:
a first data receiving circuit configured to receive first data through a first data bus; and
a first parallelizer configured to synchronize the first data to the plurality of internal clock signals to generate a plurality of first internal data signals.
18. The semiconductor apparatus of claim 17 , further comprising:
a second data receiving circuit configured to receive second data through a second data bus; and
a second parallelizer configured to synchronize the second data to the plurality of internal clock signals to generate a plurality of second internal data signals.