Emulating memory sub-systems that have different performance characteristics

1. A method comprising:

receiving, by a processing device, a request to emulate a characteristic of a target memory sub-system;

identifying a candidate configuration that generates a load on a memory sub-system of a host system to decrease a characteristics of the memory sub-system of the host system; and

updating a configuration of the host system based at least on the candidate configuration, wherein the updated configuration changes the memory sub-system of the host system to emulate the characteristic of the target memory sub-system.

2. The method of claim 1 , wherein the memory sub-system of the host system comprises Dynamic Random Access Memory (DRAM) and wherein the target memory sub-system comprises Non-Volatile Memory (NVRAM) that is absent from the host system.

3. The method of claim 1 , wherein the characteristic of the target memory sub-system comprises a set of performance characteristics comprising at least one of a read latency, a write latency, or a transfer bandwidth.

4. The method of claim 1 , wherein the host system comprises a multi-socket server with a plurality of CPUs and wherein the memory sub-system comprises a plurality of memory nodes, wherein each of the plurality of CPUs uses a local memory controller to access a local memory node and uses a remote memory controller to access a remote memory node.

5. The method of claim 1 , wherein updating the configuration of the host system comprises:

starting a plurality of threads on a CPU associated with a local memory node of the memory sub-system, wherein the plurality of threads comprise a memory intensive program;

allocating memory for the plurality of threads on a remote memory node of the memory sub-system;

reducing a bus speed of a remote memory controller that provides the CPU access to the remote memory node; and

activating processor affinity to cause the plurality of threads to stay on the CPU.

6. The method of claim 1 , further comprising:

running a performance test of the host system after updating the configuration to emulate the characteristic of the target memory sub-system, wherein the updated configuration applies a load on the memory sub-system using a first CPU and wherein the performance test applies an additional load on the memory sub-system using a second CPU.

7. The method of claim 1 , wherein the candidate configuration corresponds to a point in a configuration parameter space and comprises a particular combination of parameter values, wherein the configuration parameter space represents available parameter values of the host system.

8. The method of claim 1 , further comprising determining a plurality of candidate configurations based on available parameter values of the host system, wherein the determining comprises:

determining available parameter values corresponding to different bus speeds for the memory sub-system;

determining available parameter values corresponding to a number of parallel threads that can be executed by a CPU of the host system;

determining available parameter values corresponding to an affinity of a thread to a core of the CPU;

determining available parameter values corresponding to a number of hops in a data path to a remote memory node; and

determining available parameter values corresponding to pinning memory of a thread to the remote memory node.

9. The method of claim 1 , further comprising exploring a configuration parameter space of the host system, wherein the exploring comprises:

selecting the candidate configuration based on a set of available parameter values;

updating the configuration of the host system to apply the candidate configuration;

evaluating the candidate configuration by measuring one or more characteristics of the memory sub-system; and

storing characteristic data that represents the one or more characteristics.

10. The method of claim 9 , further comprising:

generating, based on the characteristic data, one or more mathematical models that represent the characteristics of the memory sub-system as a function of the available parameter values of the host system.

11. A host system comprising:

a memory sub-system; and

a processor, operatively coupled with the memory sub-system, to perform operations comprising:

receiving a request to emulate a characteristic of a target memory sub-system;

identifying a candidate configuration that generates a load on a memory sub-system of a host system to decrease a characteristics of the memory sub-system of the host system; and

updating a configuration of the host system based at least on the candidate configuration, wherein the updated configuration changes the memory sub-system of the host system to emulate the characteristic of the target memory sub-system.

12. The host system of claim 11 , wherein the memory sub-system of the host system comprises Dynamic Random Access Memory (DRAM) and wherein the target memory sub-system comprises Non-Volatile Memory (NVRAM) that is absent from the host system.

13. The host system of claim 11 , wherein the characteristic of the target memory sub-system comprises a set of performance characteristics comprising at least one of a read latency, a write latency, or a transfer bandwidth.

14. The host system of claim 11 , wherein the host system comprises a multi-socket server with a plurality of CPUs and wherein the memory sub-system comprises a plurality of memory nodes, wherein each of the plurality of CPUs uses a local memory controller to access a local memory node and uses a remote memory controller to access a remote memory node.

15. The host system of claim 11 , wherein the candidate configuration corresponds to a point in a configuration parameter space and comprises a particular combination of parameter values, wherein the configuration parameter space represents available parameter values of the host system.

16. A non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

receiving a request to emulate a characteristic of a target memory sub-system;

identifying a candidate configuration that generates a load on a memory sub-system of a host system to decrease a characteristics of the memory sub-system of the host system; and

updating a configuration of the host system based at least on the candidate configuration, wherein the updated configuration changes the memory sub-system of the host system to emulate the characteristic of the target memory sub-system.

17. The non-transitory computer-readable medium of claim 16 , wherein the memory sub-system of the host system comprises Dynamic Random Access Memory (DRAM) and wherein the target memory sub-system comprises Non-Volatile Memory (NVRAM) that is absent from the host system.

18. The non-transitory computer-readable medium of claim 16 , wherein the characteristic of the target memory sub-system comprises a set of performance characteristics comprising at least one of a read latency, a write latency, and a transfer bandwidth.

19. The non-transitory computer-readable medium of claim 16 , wherein the host system comprises a multi-socket server with a plurality of CPUs and wherein the memory sub-system comprises a plurality of memory nodes, wherein each of the plurality of CPUs uses a local memory controller to access a local memory node and uses a remote memory controller to access a remote memory node.

20. The non-transitory computer-readable medium of claim 16 , the operations further comprising:

running a performance test of the host system after updating the configuration to emulate the characteristic of the target memory sub-system, wherein the updated configuration applies a load on the memory sub-system using a first CPU and wherein the performance test applies an additional load on the memory sub-system using a second CPU.