Semiconductor device and method of fabricating the same
A semiconductor device including memory cells that are three-dimensionally arranged is provided. The semiconductor device includes: a stack structure including first and second layers, which are sequentially stacked on a substrate, the first layer including first and second semiconductor patterns, which are spaced apart from each other and extend in a first direction, and a first bitline, which extends in a second direction different from the first direction and is electrically connected to the first and second semiconductor patterns, the second layer including third and fourth semiconductor patterns, which are spaced apart from each other and extend in the first direction, and a second bitline, which extends in the second direction and is electrically connected to the third and fourth semiconductor patterns, and each of the first through fourth semiconductor patterns including a source, a channel, a drain, and a bottom electrode; a first wordline connecting the channels of the first and third semiconductor patterns in a vertical direction; a second wordline connecting the channels of the second and fourth semiconductor patterns in the vertical direction.
1 . A semiconductor device comprising:
a stack structure including first and second layers, which are sequentially stacked on a substrate, the first layer including first and second semiconductor patterns, which extend in a first direction and are spaced apart in a second direction different from the first direction, and a first bitline, which extends in the second direction and is electrically connected to the first and second semiconductor patterns, the second layer including third and fourth semiconductor patterns, which extend in the first direction and are spaced apart in the second direction, and a second bitline, which extends in the second direction and is electrically connected to the third and fourth semiconductor patterns, and each of the first through fourth semiconductor patterns including a source, a channel, a drain, and a bottom electrode;
a first wordline connecting the channels of the first and third semiconductor patterns in a vertical direction, the first and third semiconductor patterns being spaced apart from each other in the vertical direction; and
a second wordline connecting the channels of the second and fourth semiconductor patterns in the vertical direction, the second and fourth semiconductor patterns being spaced apart from each other in the vertical direction,
wherein a first distance, in the first direction, between the first bitline and the first wordline differs from a second distance, in the first direction, between the first bitline and the second wordline, and the first wordline and the second wordline are spaced apart in the second direction.
2 . The semiconductor device of claim 1 , further comprising:
an isolation insulating film disposed between the first and second wordlines to extend in the vertical direction.
3 . The semiconductor device of claim 2 , wherein the isolation insulating film is in contact with the first and second wordlines and is self-aligned.
4 . The semiconductor device of claim 2 , further comprising:
an intervening semiconductor pattern extending in the first direction between the first and second semiconductor patterns,
wherein the isolation insulating film is formed to penetrate the intervening semiconductor pattern.
5 . The semiconductor device of claim 2 , wherein a width, in the first direction, of the isolation insulating film is greater than a width, in the first direction, of the first or second wordline.
6 . The semiconductor device of claim 1 , wherein
is the source, the channel, and the drain of the first semiconductor pattern are positioned on a first side of the bottom electrode of the first semiconductor pattern, and
the isolation insulating film is positioned on a second side of the bottom electrode of the first semiconductor pattern.
7 . The semiconductor device of claim 1 , wherein
the first layer further includes a fifth semiconductor pattern, which extends in the first direction,
the first, second, and fifth semiconductor patterns are sequentially arranged,
the second layer further includes a sixth semiconductor pattern, which extends in the first direction,
the third, fourth, and sixth semiconductor patterns are sequentially arranged,
each of the fifth and sixth semiconductor patterns includes a source, a channel, a drain, and a bottom electrode, and
the semiconductor device further comprises a third wordline connecting the channels of the fifth and sixth semiconductor patterns in the vertical direction.
8 . The semiconductor device of claim 7 , wherein an imaginary line connecting centers of the first and third wordlines does not overlap with the second wordline.
9 . The semiconductor device of claim 1 , wherein
the first layer further includes a seventh semiconductor pattern, which extends in the first direction between the first and second semiconductor patterns, and a third bitline, which is electrically connected to the seventh semiconductor pattern,
the first bitline is disposed on a first side of the first semiconductor pattern, and
the third bitline is disposed on a second side of the seventh semiconductor pattern.
10 . A semiconductor device comprising:
a stack structure including first and second layers, which are sequentially stacked on a substrate, the first layer including first and second semiconductor patterns, which are spaced apart from each other and extend in a first direction, and a first bitline, which extends in a second direction different from the first direction and is electrically connected to the first and second semiconductor patterns, the second layer including third and fourth semiconductor patterns, which are spaced apart from each other and extend in the first direction, and a second bitline, which extends in the second direction and is electrically connected to the third and fourth semiconductor patterns, and each of the first through fourth semiconductor patterns including a source, a channel, a drain, and a bottom electrode;
a first wordline connecting the channels of the first and third semiconductor patterns in a vertical direction;
a second wordline connecting the channels of the second and fourth semiconductor patterns in the vertical direction; and
a gate insulating film surrounding four sides of each of the channels of each of the first through fourth semiconductor patterns, on each of the first through fourth semiconductor patterns,
wherein a first distance, in the first direction, between the first bitline and the first wordline differs from a second distance, in the first direction, between the first bitline and the second wordline.
11 . A semiconductor device comprising:
a stack structure including first and second layers, which are sequentially stacked on a substrate, the first layer including first and second semiconductor patterns, which are spaced apart from each other and extend in a first direction, and a first bitline, which extends in a second direction different from the first direction and is electrically connected to the first and second semiconductor patterns, the second layer including third and fourth semiconductor patterns, which are spaced apart from each other and extend in the first direction, and a second bitline, which extends in the second direction and is electrically connected to the third and fourth semiconductor patterns, and each of the first through fourth semiconductor patterns including a source, a channel, a drain, and a bottom electrode;
a first wordline connecting the channels of the first and third semiconductor patterns in a vertical direction; and
a second wordline connecting the channels of the second and fourth semiconductor patterns in the vertical direction,
wherein a first distance, in the first direction, between the first bitline and the first wordline differs from a second distance, in the first direction, between the first bitline and the second wordline,
wherein the first and second layers are arranged in a stepwise shape so that the first bitline of the first layer includes an exposed region exposed by the second layer, and
wherein the semiconductor device further comprises a bitline contact in contact with the exposed region of the first bitline.