Truth table extension for stacked memory systems
Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.
1. A logic die for a storage device, the logic die comprising:
a first interface to communicate with a stack of memory die of the storage device;
a second interface configured to couple with a host device;
a second memory accessible from the second interface; and
processing circuitry configured to:
initiate a first operation for the stack of memory die in response to a first request from the host device, wherein the first request uses a first command/address bus of the second interface to identify the first operation;
initiate a second operation for the stack of memory die in response to a second request from the host device, wherein the second request uses a second command/address bus of the second interface to identify the second operation as a read operation or a write operation; and
initiate a third operation for the second memory in response to a third request from the host device, wherein the third request uses both the first command/address bus and the second command/address bus to identify the third operation for the second memory.
2. The logic die of claim 1 , wherein the stack of memory die comprise a dynamic random-access memory (DRAM) die, and the second memory comprises a static random-access memory (SRAM) device.
3. The logic die of claim 1 , wherein the first request is communicated by the second interface using the first command/address bus and without using the second command/address bus, and wherein the second request is communicated by the second interface using the second command/address bus and without using the first command/address bus.
4. The logic die of claim 1 , wherein the first operation for the stack of memory die is other than a read operation and is other than a write operation.
5. The logic die of claim 4 , wherein the first operation is one or more of a pre-charge operation, a refresh operation, or a power-down operation for the stack of memory die.
6. The logic die of claim 1 , wherein the third request uses respective different numbers of bits on the first and second command/address busses to identify the third operation for the second memory.
7. The logic die of claim 1 , wherein the third operation includes:
two or more leading bits of a command on the first command/address bus set to identify the third request is for the second memory; and
two or more leading bits of a command on the second command/address bus to identify the third request is for the second memory.
8. The logic die of claim 7 , wherein the third operation includes a third bit of the command on the second command/address bus that identifies the third request as a read operation for the second memory.
9. The logic die of claim 7 , wherein the third operation includes a third bit of the command on the second command/address bus that identifies the third request as a write operation for the second memory.
10. The logic die of claim 7 , wherein the two or more leading bits of the command on the first command/address bus includes a first three bits set to alternating logic levels; and
wherein the two or more leading bits of the command on the second command/address bus includes a first two bits set to different logic levels.
11. The logic die of claim 7 , wherein the two or more leading bits of the command on the first command/address bus includes a first three bits set to logic HIGH, LOW, HIGH, respectively; and
wherein the two or more leading bits of the command on the second command/address bus includes a first two bits set to logic LOW, HIGH, respectively.
12. The logic die of claim 1 , wherein in response to the second or third operation, the processing circuitry is configured to use, as a target data location, a data bus of the second interface or a buffer of the logic die.
13. The logic die of claim 1 , wherein in response to the second or third operation and based on a particular bit value of a command on the second command/address bus, the processing circuitry is configured to use a data bus of the second interface or a buffer of the logic die as a target data location.
14. A method comprising:
executing a first memory operation at a memory device having a stack of memory die in response to a first command on a first command/address bus;
executing a second memory operation at the memory device in response to a second command on a second command/address bus; and
executing a third memory operation of the memory device in response to a third command on the first command/address bus and the second command/address bus, wherein the third memory operation is configured to access second memory of a logic die of the memory device, wherein the second memory is other than the stack of memory die.
15. The method of claim 14 , wherein executing the first or second memory operation at the memory device includes using a dynamic random-access memory (DRAM).
16. The method of claim 15 , wherein executing the third memory operation to access the second memory includes accessing a static random-access memory (SRAM).
17. The method of claim 15 , wherein the executing the third memory operation includes setting a particular bit of the second command/address bus to one of a first state or a second state to indicate a data target location for the third memory operation, wherein the data target location is one of a buffer of the logic die or a host data bus that couples the logic die with a host device.
18. The method of claim 14 , wherein the third command comprises a portion of an address for the second memory on the first command/address bus and another portion of the address for the second memory on the second command/address bus.
19. The method of claim 14 , wherein the third command includes a leading first three bits on the first command/address bus set to alternating logic levels.
20. The method of claim 19 , wherein the third command includes the leading first three bits on the first command/address bus set to logic HIGH, LOW, HIGH, respectively, and the third command includes a leading first two bits on the second command/address bus set to logic LOW, HIGH, respectively.