System and method for time-of-flight determination using categorization of both code and phase in received signal

1. A method for detecting a probe signal at an estimated code delay and an estimated doppler frequency, comprising:

(i) dividing a period of the probe signal into sections each of a predetermined duration;

(ii) assigning to each section one of a plurality of code categories, each code category being indicative of a signal pattern of the probe signal within the section;

(iii) selecting a plurality of phase categories for a sinusoidal signal, each phase category being indicative of a range of phases in the sinusoidal signal;

(iv) receiving a signal from which the probe signal is to be detected;

(v) dividing the received signal into sections each of the predetermined duration;

(v) assigning each section of the received signal both a corresponding code category and a corresponding phase category, based respectively on the estimated code delay and the doppler frequency; and

(vi) separately accumulating sections of the received signal according to the assigned code and phase categories of each section.

2. The method of claim 1 , wherein the predetermined duration is up to one chip.

3. The method of claim 1 , wherein each section of the received signal comprises a plurality of samples.

4. The method of claim 3 , wherein each sample includes an in-phase component and a quadrature component.

5. The method of claim 1 , wherein the probe signal has modulated thereon repeated cycles of a pseudorandom code.

6. An integrated circuit for detecting a probe signal in a received signal, comprising:

a memory circuit for storing one or more sections of the received signal, each section having a pre-determined duration;

a plurality of processing circuits, each including one or more individually addressable accumulators; and

a dispatch circuit including (i) storage elements for storing a plurality of code categories each being assigned to a corresponding one of consecutive sections of the probe signal, each section of the probe signal having the predetermined duration and each code category being indicative of a signal transition pattern of the probe signal within the corresponding section; and (ii) a code counter circuit which maps each section of the received signal to a corresponding one of the code categories in the storage elements based on an estimated code delay between the probe signal and the received signal; and (iii) a phase counter circuit which maps each section of the received signal to a corresponding one of a plurality of phase categories of a sinusoidal signal based on an estimated doppler frequency between the received signal and the probe signal, wherein the dispatch circuit maps each section of the received signal to one of the addressable accumulators based on the corresponding code category and the corresponding phase category.

7. The integrated circuit of claim 6 , further comprising a control circuit which causes the code categories of the probe signal be stored into the storage elements.

8. The integrated circuit of claim 7 , wherein the dispatch circuit further comprises a code category generation circuit which determines the code categories in the storage elements based on a pseudorandom code specified by the control circuit.

9. The integrated circuit of claim 8 , wherein the dispatch circuit further comprises a gold code generator circuit.

10. The integrated circuit of claim 7 , wherein the control circuit comprises a microprocessor or microcontroller.

11. The integrated circuit of claim 10 , wherein the microprocessor or microcontroller is integrated into the integrated circuit in a system-on-a-chip manner.

12. The integrated circuit of claim 6 , wherein the dispatch circuit includes multiple sets of storage elements, code counter circuits and phase counter circuits for detecting multiple probe signals, multiple estimated code delays and multiple estimated doppler frequencies.

13. The integrated circuit of claim 6 , wherein the predetermined duration is up to one chip.

14. The integrated circuit of claim 6 , wherein each section of the received signal comprises a plurality of samples.

15. The integrated circuit of claim 14 , wherein each sample includes an in-phase component and a quadrature component.

16. The integrated circuit of claim 15 , wherein each accumulator separately accumulates the in-phase and quadrature components of each sample separately, the accumulator further comprising vector registers, vector summers and vector accumulation elements for the separate accumulations.

17. The method of claim 6 , wherein the probe signal has modulated thereon repeated cycles of a pseudorandom code.