IP Library › Granted Patent US 12,255,754
Granted Patent B2
US 12,255,754 · App. 18/101,342 · Granted Mar 18, 2025

High-speed, half-duplex communication with standard microcontroller

Inventors: Florent Guichard (Nantes, FR); Thomas Girard (Nantes, FR); Freddy Excoffier (Nantes, FR)
Assignee: SERCEL
H04L12/40032H04L25/4904
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Quick Facts
Patent No.
US 12,255,754
App. No.
18/101,342
Granted
Mar 18, 2025
Kind
B2
Abstract

A communication system includes a node configured to collect ambient data with a sensor, and a docking station configured to couple to the node and to establish a communication path with the node through only one signal along one or two wires. The node includes a first module configured to use a first data communication protocol for receiving commands from the docking station along the communication path, and a second module configured to use a second data communication protocol for sending the ambient data to the docking station along the communication path. The first data communication protocol is different from the second data communication protocol, the first data communication protocol is asynchronous and the second data communication protocol is a modified synchronous protocol.

Claims (61)

1. A communication system comprising:

a node configured to collect ambient data with a sensor; and

a docking station configured to couple to the node and to establish a communication path with the node through only one signal along one or two wires,

wherein the node includes,

a first module configured to use a first data communication protocol for receiving commands from the docking station along the communication path, and

a second module configured to use a second data communication protocol for sending the ambient data to the docking station along the communication path,

wherein the first data communication protocol is different from the second data communication protocol, the first data communication protocol is asynchronous and the second data communication protocol is a modified synchronous protocol,

wherein the first data communication protocol is a Universal Asynchronous Receiver/Transmitter, UART, protocol, and the second data communication protocol is a Serial Peripheral Interface, SPI, protocol

wherein the second module is an SPI module that is modified to not transmit a clock signal to the docking station,

wherein the SPI module is configured to not send a chipselect signal to the docking station; and

wherein the node includes a legacy microcontroller, which is not configured to implement USB high speed, 100 Mbits Ethernet MAC or WiFi protocols.

2. The system of claim 1 , wherein the first module is configured to not send a clock signal.

3. The system of claim 2 , wherein the second module is configured to generate a clock signal but the clock signal is not sent from the node to the docking station.

4. The system of claim 1 , wherein the node further comprises:

a half-duplex transceiver functionally connected to the first and second modules and configured to transform a full duplex signal from the second module to a half-duplex signal.

5. The system of claim 1 , wherein the node further includes a field programable gate array, FPGA, connected between a microprocessor and a half-duplex transceiver.

6. The system of claim 1 , wherein the docking station includes:

a half-duplex transceiver connected to the only one or two wires;

a field programable gate array, FPGA, functionally connected to the half-duplex transceiver; and

a microprocessor functionally connected to the FPGA,

wherein the FPGA is configured to decode the ambient data received from the node.

7. The system of claim 1 , wherein the node includes a first plug and the docking station includes a second plug and the first plug mechanically engages the second plug to establish the communication path.

8. The system of claim 1 , wherein the node is a seismic node and the sensor is an accelerometer or geophone.

9. A seismic data acquisition node comprising:

a housing;

a seismic sensor attached to the housing; and

a microprocessor configured to receive seismic data collected by the seismic sensor and transmit the seismic data to a docking station,

wherein the node is configured to establish a communication path with the docking station through only a single signal along one or two wires, and

wherein the microprocessor includes:

a first module configured to use a first data communication protocol for receiving commands from the docking station along the communication path, and

a second module configured to use a second data communication protocol for sending the seismic data to the docking station along the communication path,

wherein the first data communication protocol is different from the second data communication protocol, the first data communication protocol is asynchronous, and the second data communication protocol is a modified synchronous protocol,

wherein the first data communication protocol is a Universal Asynchronous Receiver/Transmitter, UART, protocol, and the second data communication protocol is a Serial Peripheral Interface, SPI, protocol

wherein the second module is an SPI module that is modified to not transmit a clock signal to the docking station,

wherein the SPI module is configured to not send a chipselect signal to the docking station; and

wherein the node includes a legacy microcontroller, which is not configured to implement USB high speed, 100 Mbits Ethernet MAC or WiFi protocols.

10. The node of claim 9 , wherein the first module is configured to not send a clock signal.

11. The node of claim 10 , wherein the second module is configured to generate a clock signal, but the second module is configured to not send the clock signal to the docking station.

12. The node of claim 9 , further comprising:

a half-duplex transceiver functionally connected to the first and second modules and configured to transform a full duplex signal from the second module to a half-duplex signal.

13. A docking station for receiving seismic data from a seismic node, the docking station comprising:

a housing;

a half-duplex transceiver located in the housing and connected to the seismic node through a communication path having only one or two wires;

a field programable gate array, FPGA, located in the housing and functionally connected to the half-duplex transceiver; and

a microprocessor located in the housing and functionally connected to the FPGA,

wherein the FPGA is configured to decode the seismic data received from the node along the communication path using a Serial Peripheral Interface, SPI, protocol,

wherein the seismic node includes an SPI module that is modified to not transmit a clock signal to the docking station,

wherein the SPI module is configured to not send a chipselect signal to the docking station; and

wherein the seismic node includes a legacy microcontroller, which is not configured to implement USB high speed, 100 Mbits Ethernet MAC or WiFi protocols.

14. The docking station of claim 12 , wherein the FPGA is configured to not transmit a clock signal and a chipselect signal to the node.

15. A communication system comprising:

a node configured to collect ambient data with a sensor; and

a docking station configured to couple to the node and to establish a communication path with the node through only one signal along one or two wires,

wherein the node includes,

a first module configured to use a data communication protocol for receiving commands from the docking station along the communication path, and

a second module configured to use a same data communication protocol for sending the ambient data to the docking station along the communication path,

wherein the data communication protocol is a modified synchronous protocol in which the node and the docking station do not exchange a clock signal,

wherein the data communication protocol is a Serial Peripheral Interface, SPI, protocol

wherein the second module is an SPI module that is modified to not transmit a clock signal to the docking station,

wherein the SPI module is configured to not send a chipselect signal to the docking station; and

wherein the node includes a legacy microcontroller, which is not configured to implement USB high speed, 100 Mbits Ethernet MAC or WiFi protocols.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2023
From: GUICHARD, FLORENT; GIRARD, THOMAS; EXCOFFIER, FREDDY
To: SERCEL
Reel/Frame 062570/0244 →
Continuity (1)
Related Publication 20240250844A1 · Jul 25, 2024
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