IP Library › Granted Patent US 12,316,534
Granted Patent B2
US 12,316,534 · App. 18/101,677 · Granted May 27, 2025

Latency sensitive network plane via SR flex algorithm for layer 1 services

Inventors: Bhupendra Yadav (Ottawa, CA); Prabhu Vaithilingam (Kanata, CA); Gerald Smallegange (Stittsville, CA); Alwyn Joy George (New Delhi, IN)
Assignee: Ciena Corporation
H04L45/34H04L45/121
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Quick Facts
Patent No.
US 12,316,534
App. No.
18/101,677
Granted
May 27, 2025
Kind
B2
Abstract

Systems and methods include maintaining a network plane in Segment Routing (SR) Flexible Algorithm having a Flexible Algorithm Definition (FAD) based on latency; receiving a request for a service over a SR network where the service is sensitive to a specific latency; and determining a label stack including one or more Segment Identifiers (SID) for the service, with the one or more SIDs based on the network plane in SR Flexible Algorithm. This can be used for Private Line Emulation (PLE) services and Circuit Emulation (CEM) services over SR, ensuring latency while not requiring large label stacks.

Claims (28)

1. A processing device comprising:

at least one processor and memory storing instructions that, when executed, cause the at least one processor to

maintain a network plane in Segment Routing (SR) Flexible Algorithm having a Flexible Algorithm Definition (FAD) based on latency, wherein the FAD includes one or more of a latency range, a latency value, and a latency tolerance, for each of a plurality of links in the SR network, and wherein values for latency are based on measurements at lower layers over which the SR network operates,

receive a request for a service over a SR network where the service is sensitive to a specific latency, and

determine a label stack including one or more Segment Identifiers (SID) for the service, with the one or more SIDs based on the network plane in SR Flexible Algorithm.

2. The processing device of claim 1 , wherein the instructions that, when executed, further cause the at least one processor to

receive Link State Advertisements (LSA) with a Type-Length-Value (TLV) and a sub-TLV for the FAD.

3. The processing device of claim 2 , wherein the TLV specifies the FAD and the sub-TLV includes one or more values for latency on a given link in the SR network.

4. The processing device of claim 1 , wherein the FAD is maintained over time based on network events and flooding of adjusted latency information.

5. The processing device of claim 1 , wherein the service is one of a Private Line Emulation (PLE) service and a Circuit Emulation (CEM) service.

6. A non-transitory computer-readable medium comprising instructions that, when executed, cause at least one processor to perform steps of:

maintaining a network plane in Segment Routing (SR) Flexible Algorithm having a Flexible Algorithm Definition (FAD) based on latency, wherein the FAD includes one or more of a latency range, a latency value, and a latency tolerance, for each of a plurality of links in the SR network, and wherein values for latency are based on measurements at lower layers over which the SR network operates;

receiving a request for a service over a SR network where the service is sensitive to a specific latency; and

determining a label stack including one or more Segment Identifiers (SID) for the service, with the one or more SIDs based on the network plane in SR Flexible Algorithm.

7. The non-transitory computer-readable medium of claim 6 , wherein the steps further include

receiving Link State Advertisements (LSA) with a Type-Length-Value (TLV) and a sub-TLV for the FAD.

8. The non-transitory computer-readable medium of claim 7 , wherein the TLV specifies the FAD and the sub-TLV includes one or more values for latency on a given link in the SR network.

9. The non-transitory computer-readable medium of claim 6 , wherein the FAD is maintained overtime based on network events and flooding of adjusted latency information.

10. The non-transitory computer-readable medium of claim 6 , wherein the service is one of a Private Line Emulation (PLE) service and a Circuit Emulation (CEM) service.

11. A method comprising steps of:

maintaining a network plane in Segment Routing (SR) Flexible Algorithm having a Flexible Algorithm Definition (FAD) based on latency, wherein the FAD is maintained over time based on network events and flooding of adjusted latency information;

receiving a request for a service over a SR network where the service is sensitive to a specific latency; and

determining a label stack including one or more Segment Identifiers (SID) for the service, with the one or more SIDs based on the network plane in SR Flexible Algorithm.

12. The method of claim 11 , wherein the steps further include

receiving Link State Advertisements (LSA) with a Type-Length-Value (TLV) and a sub-TLV for the FAD.

13. The method of claim 12 , wherein the TLV specifies the FAD and the sub-TLV includes one or more values for latency on a given link in the SR network.

14. The method of claim 11 , wherein the FAD includes one or more of a latency range, a latency value, and a latency tolerance, for each of a plurality of links in the SR network.

15. The method of claim 14 , wherein values for latency are based on measurements at lower layers over which the SR network operates.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2023
From: YADAV, BHUPENDRA; VAITHILINGAM, PRABHU; SMALLEGANGE, GERALD; GEORGE, ALWYN JOY
To: CIENA CORPORATION
Reel/Frame 062495/0928 →
Priority Claims (1)
IN 202211072158 · Dec 14, 2022 · national
Continuity (1)
Related Publication 20240205142A1 · Jun 20, 2024
References Cited (17)
US 7609620B2 · Raj et al. · 2009 [cited by applicant]
US 7969898B1 · Raj et al. · 2011 [cited by applicant]
US 8116308B2 · Ellis et al. · 2012 [cited by applicant]
US 8504727B2 · Mohan et al. · 2013 [cited by applicant]
US 8576708B2 · Gandhi et al. · 2013 [cited by applicant]
US 9049142B1 · Osborne et al. · 2015 [cited by applicant]
US 9197493B2 · Holness et al. · 2015 [cited by applicant]
US 10158448B2 · Prakash et al. · 2018 [cited by applicant]
US 10469367B2 · Filsfils et al. · 2019 [cited by applicant]
US 20070268817A1 · Smallegange et al. · 2007 [cited by applicant]
US 20080273472A1 · Bashford et al. · 2008 [cited by applicant]
US 20090190610A1 · Pirbhai · 2009 [cited by examiner]
US 20150365294A1 · Khan et al. · 2015 [cited by applicant]
US 20210266251A1 · Yadav et al. · 2021 [cited by applicant]
US 20220247663A1 · Van de Velde · 2022 [cited by examiner]
US 20220303212A1 · Chan · 2022 [cited by examiner]
EP 3813310A1 · 2021 [cited by applicant]