IP Library Granted Patent US 12,399,202
Granted Patent B2
US 12,399,202 · App. 18/103,168 · Granted Aug 26, 2025

Impedance controlled AFE

Inventors: Arnaud Toni (San Diego, CA); Gol Nagdebe (San Diego, CA)
Assignee: Endura IP Holdings Ltd.
G01R27/2605H03K3/037H03K19/20
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Quick Facts
Patent No.
US 12,399,202
App. No.
18/103,168
Granted
Aug 26, 2025
Kind
B2
Abstract

An analog front-end (AFE) for an impedance sensor uses digitally controlled impedances to modulate a differential input from an impedance-based sensor. The digitally controlled impedances may be coupled between the differential input and one or more reference voltages. In some embodiments use of the digitally controlled impedances may allow for omission of a preamplifier from the AFE, or a reduction in gain of the preamplifier, reducing noise associated with the preamplifier.

Claims (17)

1. An impedance controlled analog front end (AFE) for an impedance-based sensor, comprising:

a filter with a first input of a differential input coupled to a first output of a differential output of an impedance-based sensor and a second input of the differential input coupled to a second output of the differential output of the impedance-based sensor;

an analog-to-digital converter (ADC) with an input coupled to an output of the filter, the ADC configured to provide a digital output; and

a first digitally controlled impedance coupling the first input to the filter to a reference voltage, and a second digitally controlled impedance coupling the second input to the filter to the reference voltage, the impedance of the first digitally controlled impedance being based on the digital output of the ADC.

2. The impedance controlled AFE of claim 1 , wherein the impedance-based sensor is a capacitive sensor, and the first digitally controlled impedance is a first digitally controlled capacitance.

3. The impedance controlled AFE of claim 2 , wherein the first digitally controlled capacitance comprises a first digitally controlled varactor.

4. The impedance controlled AFE of claim 3 , wherein the first digital controlled varactor includes a plurality of cells, each cell including a capacitance coupled between an output of the impedance-based sensor and one or more reference voltages.

5. The impedance controlled AFE of claim 4 , wherein the one or more reference voltages consists of three reference voltages.

6. The impedance controlled AFE of claim 2 , wherein the digitally controlled capacitance comprises a segmented charge digitally controlled impedance.

7. The impedance controlled AFE of claim 1 , wherein the ADC comprises a quantizer.

8. The impedance controlled AFE of claim 1 , wherein the ADC comprises a voltage-controlled oscillator (VCO) quantizer.

9. The impedance controlled AFE of claim 1 , wherein the ADC comprises a phase quantizer.

10. The impedance controlled AFE of claim 1 , wherein the filter comprises an integrator.

11. The impedance controlled AFE of claim 1 , wherein the impedance-based sensor is a capacitive sensor, and the first digitally controlled impedance is a first digitally controlled capacitance and the second digitally controlled impedance is a second digitally controlled capacitance.

12. The impedance controlled AFE of claim 11 , wherein the first digitally controlled capacitance comprises a first digitally controlled varactor and the second digitally controlled capacitance comprises a second digitally controlled varactor.

13. The impedance controlled AFE of claim 12 , wherein each of the digital controlled varactors includes a plurality of cells, each cell including a capacitance coupled between an output of the impedance-based sensor and one or more reference voltages.

14. The impedance controlled AFE of claim 1 , where the impedance of the second digitally controlled impedance is based on the digital output of the ADC.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2023
From: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
To: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
Reel/Frame 063364/0702 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2023
From: TONI, ARNAUD; NAGDEBE, GOL
To: ENDURA TECHNOLOGIES (INTERNATIONAL) LIMITED
Reel/Frame 063062/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2023
From: ENDURA TECHNOLOGIES (INTERNATIONAL) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
Reel/Frame 063062/0236 →
Continuity (2)
Provisional Application 63267260 · Jan 28, 2022
Related Publication 20230243877A1 · Aug 3, 2023
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