Continuous time ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array
A continuous time ΔΣ analog-to-digital converter with mitigation bit shifting multiplex array including a loop filter, a VCO responsive to analog signal configured to adjust the output frequency based on the magnitude of the analog signal and produce a digital output, a multi-stage phase quantizer responsive to the digital output configured to determine the phase of the VCO by comparing the phase of the VCO for a particular sample to a reference phase at said particular sample and generate a quantized phase difference value, and a multiplexer array coupled to the multi-stage phase quantizer configured to shift selected misaligned bits of the quantized phase difference value by a predetermined amount of bits to mitigate bit shifting of the multi-stage phase quantizer.
1. A continuous time ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array comprising:
a loop filter,
a VCO responsive to analog signal configured to adjust the output frequency based on the magnitude of the analog signal and produce a digital output;
a multi-stage phase quantizer responsive to the digital output configured to determine the phase of the VCO by comparing the phase of the VCO for a particular sample to a reference phase at the particular sample and generate a quantized phase difference value; and
a multiplexer array coupled to the multi-stage phase quantizer configured to shift selected misaligned bits of the quantized phase difference value by a predetermined amount of bits to mitigate bit shifting of the multi-stage phase quantizer.
2. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 1 in which the multi-stage phase quantizer includes a plurality of phase quantizers.
3. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 2 in which the multiplexer array includes a plurality of multiplexers coupled to selected phase quantizers of the multi-stage phase quantizer.
4. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 1 in which the selected multiplexers each include two inputs and one output.
5. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 4 in which the selected multiplexers are coupled to selected phase quantizers and cross-coupled to different selected phase quantizers.
6. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 5 in which the VCO, the multi-stage phase quantizer and the multiplexer array includes an even number of stages.
7. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 6 in which the multiplexer array includes a least one multiplexer having one input and one output.
8. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 7 in which the at least one multiplexer is coupled to a selected phase quantizer.
9. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 5 in which the VCO, the multi-stage phase quantizer and the multiplexer array each include an odd number of stages.
10. The ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array of claim 1 in which the selected misaligned bits includes the number of bits corresponds to half the number of stages of the multistage phase quantizer rounded up.
11. A method for mitigating bit shifting for a continuous time ΔΣ analog-to-digital converter, the method comprising the steps of:
providing a loop filter;
providing a VCO responsive to an analog signal;
adjusting the output frequency based on the magnitude of the analog signal and producing a digital output;
providing a multi-stage phase quantizer responsive to the digital output;
determining the phase of the VCO by comparing the phase of the VCO for a particular sample to a reference sample at the particular sample;
generating a quantized phase difference value;
providing a multiplexer array coupled to the multi-stage phase quantizer; and
shifting selected misaligned bits of the quantized phase difference value by a predetermined amount of bits to mitigate bit shifting of the multi-stage phase quantizer.
12. The method of claim 11 further including the step of coupling selected multiplexers of the multiplex array to selected phase quantizers of the multi-stage phase quantizer and cross coupling the selected multiplexes to different phase quantizers.
13. The method of claim 11 further including the step of shifting misaligned bits output by the multi-stage phase quantizer to be equal to half the number of stages of the multistage phase quantizer rounded up.