Neural memory array storing synapsis weights in differential cell pairs
Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).
1. A system comprising:
a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and
a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column;
wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).
2. The system of claim 1 , further comprising source line pulldown bit lines.
3. The system of claim 1 , further comprising redundant columns.
4. The system of claim 3 , wherein the redundant columns are used to remap weights from a W+ or W− column.
5. The system of claim 4 , wherein the redundant columns are used to remap weights to avoid floating gate to floating gate coupling.
6. The system of claim 4 , wherein the redundant columns are used to remap weights to distribute power more evenly among the columns.
7. The system of claim 4 , wherein the redundant columns are used to remap weight from noisy or defective cells.
8. The system of claim 1 , wherein the non-volatile memory cells in the first array and the second array are split gate flash memory cells.
9. The system of claim 1 , wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.
10. The system of claim 1 , further comprising a summer for summing outputs from one or more bit lines.
11. The system of claim 10 , wherein the summer is adjustable based on a variable resistor.
12. The system of claim 10 , wherein the summer is adjustable based on a variable capacitor.
13. The system of claim 10 , wherein the summer comprises a switched capacitor circuit and an operational amplifier.
14. The system of claim 10 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
15. The system of claim 14 , wherein the analog-to-digital converter comprises a successive approximation register.
16. The system of claim 14 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.